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Low 50碌A(chǔ) Sleep Mode Current
DESCRIPTION
The UC3573 is a Buck pulse width modulator which steps down and regu-
lates a positive input voltage. The chip is optimized for use in a single in-
ductor buck switching converter employing an external PMOS switch. The
block diagram consists of a precision reference, an error amplifier config-
ured for voltage mode operation, an oscillator, a PWM comparator with
latching logic, and a 0.5A peak gate driver. The UC3573 includes an
undervoltage lockout circuit to insure sufficient input supply voltage is pres-
ent before any switching activity can occur, and a pulse-by-pulse current
limit. Input current can be sensed and limited to a user determined maxi-
mum value. In addition, a sleep comparator interfaces to the UVLO circuit
which turns the chip off when the input voltage is below the UVLO thresh-
old. This reduces the supply current to only 50碌A(chǔ), making the UC3573
ideal for battery powered applications.
BLOCK DIAGRAM
UDG-94106-1
SLUS346 - APRIL 1999