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UC1715 Datasheet

  • UC1715

  • Complementary Switch FET Drivers

  • 8頁(yè)

  • TI

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UC1714/5
UC2714/5
UC3714/5
Complementary Switch FET Drivers
FEATURES
鈥?/div>
Single Input (PWM and TTL
Compatible)
鈥?/div>
High Current Power FET Driver, 1.0A
Source/2A Sink
鈥?/div>
Auxiliary Output FET Driver, 0.5A
Source/1A Sink
鈥?/div>
Time Delays Between Power and
Auxiliary Outputs Independently
Programmable from 50ns to 500ns
鈥?/div>
Time Delay or True Zero-Voltage
Operation Independently Configurable
for Each Output
鈥?/div>
Switching Frequency to 1MHz
鈥?/div>
Typical 50ns Propagation Delays
鈥?/div>
ENBL Pin Activates 220碌A(chǔ) Sleep
Mode
鈥?/div>
Power Output is Active Low in Sleep
Mode
鈥?/div>
Synchronous Rectifier Driver
DESCRIPTION
These two families of high speed drivers are designed to provide drive
waveforms for complementary switches. Complementary switch configura-
tions are commonly used in synchronous rectification circuits and active
clamp/reset circuits, which can provide zero voltage switching. In order to
facilitate the soft switching transitions, independently programmable de-
lays between the two output waveforms are provided on these drivers.
The delay pins also have true zero voltage sensing capability which allows
immediate activation of the corresponding switch when zero voltage is ap-
plied. These devices require a PWM-type input to operate and can be in-
terfaced with commonly available PWM controllers.
In the UC1714 series, the AUX output is inverted to allow driving a
p-channel MOSFET. In the UC1715 series, the two outputs are configured
in a true complementary fashion.
BLOCK DIAGRAM
2
PWR
50ns 鈥?00ns
INPUT
6
TIMER
S
Q
R
V
REF
50ns 鈥?00ns
TIMER
S
Q
T2
5
R
V
REF
UC1714
ONLY
T1
7
4
1
V
CC
5V
LOGIC
GATES
TIMER
REF
AUX
VCC
BIAS
ENBL 3V
GND
3
1.4V
ENBL
8
ENABLE
GND
Note: Pin numbers refer to J, N and D packages.
UDG-99028
02/99

UC1715相關(guān)型號(hào)PDF文件下載

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