鈥?/div>
High performance ULC family suitable for large-sized CPLDs and FPGAs
Conversions to over 2,000,000 FPGA gates
Pin counts to over 976 pins
Any pin鈥搊ut matched due to limited number of dedicated pads
Full range of packages: LCC/PLCC, PQFP/TQFP, fine pitch BGA, PGA/PPGA
2.5V I/O and 3.3V tolerant/compliant
Low quiescent current: <0.3 nA/gate
Available in commercial and industrial grades
0.25 mm Drawn CMOS, 5 Metal Layers
Library Optimised for Synthesis, Static Timing Analysis & Automatic Test Pattern
Generation (ATPG)
High Speed Performance:
鈥?100 ps Typical Gate Delay @2.5V
鈥?Typical 280 MHz Flip-Flop Toggle Frequency @2.5V
High System Frequency Skew Control:
鈥?Clock Tree Synthesis Software
2.5Volts & 3.3Volts Operation; Single or Dual Supply Modes
Low Power Consumption:
鈥?<0.18 碌W/Gate/MHz @2.5V
Power on Reset
Standard 2, 4, 6, 8,10, 12 and 18 mA I/Os
CMOS/TTL/PCI Interface, LVCMOS, LVTTL, PECL, PCI (33/66 MHz) levels, GTL/GTL+,
HSTL, SSTL2, SSTL3, CCT, AGP, LVDS
ESD (2 kV) and Latch-up Protected I/O
High Noise & EMC Immunity:
鈥?I/O with Slew Rate Control
鈥?Internal Decoupling
鈥?Signal Filtering between Periphery & Core
0.25 碌m ULC
Series
UA2
Preliminary
Description
The UA2 series of ULCs is well suited for conversion of large sized CPLDs and
FPGAs. Devices are implemented in high鈥損erformance CMOS technology with 0.25鈥?/div>
碌m (drawn) channel lengths, and are capable of supporting flip鈥揻lop toggle rates of
280 MHz at 2.5V, and input to output delay cells as fast as 100ps at 2.5V. The archi-
tecture of the UA2 series allows for efficient conversion of many PLD architecture and
FPGA device types with higher IO count. A compact RAM cell, along with the large
number of available gates allows the implementation of RAM in FPGA architectures
that support this feature, as well as JTAG boundary鈥搒can and scan鈥損ath testing.
Conversion to the UA2 series of ULC can provide a significant reduction in operating
power when compared to the original PLD or FPGA. This is especially true when com-
pared to many PLD and CPLD architecture devices, which typically consume 100mA
or more even when not being clocked. The UA2 series has a very low standby con-
sumption of less than 0.3 nA/gate typically commercial temp, which would yield a
standby current of 0.3 nA/gate, 0.42碌A(chǔ) on a 144,000 gates design. Operating con-
sumption is a strict function of clock frequency, which typically results in a power
reduction of 50% to 90% depending on the device being compared.
The UA2 series provides several options for output buffers, including a variety of drive
levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques
are used for improved noise immunity and reduced EMC emissions, including: several
independent power supply busses and internal decoupling for isolation; slew rate lim-
ited outputs are also available if required.
Rev. A 鈥?29-Oct-01
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