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TXC-06203AIBG Datasheet

  • TXC-06203AIBG

  • Telecommunication IC

  • 28頁(yè)

  • ETC

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PHAST-3P Device
STM-1/STS-3c SDH/SONET Overhead
Terminator with CDB/PPP UTOPIA Interface
TXC-06203
TECHNICAL OVERVIEW
FEATURES
鈥?ATM cells over SDH/SONET
- ATM cell delineation
- Single-bit error correction and multiple-bit error detection
- ATM Scrambler/descrambler option (x
43
+1)
- Idle cell discard/Cell filtering (GFC, PTI and CLP fields)
- Four-cell receive and transmit FIFOs
- Rate adaptation using idle cells
- HEC generator with optional COSET addition
鈥?PPP (IP packets) over SDH/SONET
- Octet stuffing/destuffing
- PPP Scrambler/descrambler option (x
43
+1)
- Data inversion option, Invalid frame detection
- Short frame and programmable long frame detection
- CRC-16 or CRC-32 detection/generation/pass-through option
- 256-byte receive and transmit FIFOs
鈥?Bit-serial P-ECL SDH/SONET line interface
鈥?Byte-parallel SDH/SONET line interface
鈥?Section, line and path overhead byte processing
鈥?Receive pointer tracking and false pointer detection
鈥?RAM access to section, line and path overhead bytes
鈥?Section, line and path overhead byte insertion sources:
- RAM, interfaces, ring (mate device) or receive side
鈥?Supports 1+1 or 1:N APS applications
鈥?Interfaces:
- TOH bytes with programmable byte marker pulse
- K1/K2 APS bytes
- Section data communications (D1-D3) bytes
- Line data communications (D4-D12) bytes
- POH bytes (VC-4 or each STS-1)
- Alarm Indication Port (AIP) for line/path ring operation
鈥?Terminal side 8-bit or 16-bit UTOPIA level 2 interface (with addi-
tional signals for PPP)
- Single-PHY or Multi-PHY
鈥?Intel-compatible or Motorola-compatible microprocessor interface
鈥?Boundary scan and line loopback
鈥?Single +3.3 volt, 鹵5% power supply; 5 volt input signal tolerance
鈥?256-lead plastic ball grid array package
鈥?Device driver:
- Insulates application from register access details
- Driver APIs configure and manage the PHAST-3P device
- Default configurations are provided within the driver
- One command configures all the control registers
- Driver can download the firmware code into PHAST-3P
- Similar architecture to other TXC drivers, such as the ML3M
DESCRIPTION
The TranSwitch PHAST-3P (TXC-06203) is an STM-1/STS-3c
section, line and path overhead termination device that
performs ATM and PPP PHY-layer processing. It provides
either a SDH/SONET pseudo-ECL bit-serial interface or a byte-
wide parallel interface on the line side. The serial interface
provides 155 MHz clock recovery and clock synthesis, and the
section and line overhead bytes in the data are processed. The
PHAST-3P performs pointer tracking and POH byte processing.
TOH (RSOH and MSOH) and POH bytes are provided in RAM
for microprocessor access or via TOH and POH interfaces. The
POH bytes can be inserted from RAM, the serial POH
interface, or a mate PHAST-3P device for line and path ring
applications. The terminal interface is UTOPIA level 2 for ATM
cells or level 2P for packets. UTOPIA bus width can be 8-bit or
16-bit, Single-PHY and Multi-PHY operation are supported.
For testing, the PHAST-3P provides boundary scan, B2 and B3
BER measurements, programmable BIP error mask genera-
tion, and line loopback. The device provides either Intel or
Motorola microprocessor access. Performance counters can be
configured to be saturating or roll-over. The interrupts, with
mask bits, can be programmed for positive, negative, or posi-
tive/negative alarm transitions or positive levels. A software poll-
ing register is also provided. A fully functional Device Driver is
available through TranSwitch Applications Engineering.
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Add/drop multiplexers
Data communications systems
ATM switches
Routers
Communications gateways
LINE
SIDE
Boundary Scan,
Clocks, Data,
and Control
Microprocessor
Interface
+3.3V
TERMINAL
SIDE
Bit-Serial / Byte-Parallel
Clock, Data, and Parity
Bit-Serial / Byte-Parallel
Clock, Data, and Parity
PHAST-3P
STM-1/STS-3c SDH/SONET
Overhead Terminator
with CDB/PPP UTOPIA Interface
Byte-Parallel or
Word-Parallel
CDB/PPP UTOPIA
Interface
Alarm Indication Port
Alarms
Section / Line
Transmit
Path
Section / Line
Reference
Overhead Data, Overhead Data, Datacom Data
Clock and Frame Clock and Frame Clock and Frame
and Clocks
U.S. Patents No. 4,967,405; 5,040,170;
5,141,529; 5,257,261; 5,265,096; 5,331,641; 5,724,362
U.S. and/or foreign patents issued or pending
Copyright
餂?/div>
2001 TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
PRELIMINARY
TXC-06203-MA
Ed. 4, October 2001
TranSwitch Corporation
鈥?/div>
3 Enterprise Drive
鈥?/div>
Shelton, Connecticut 06484
Tel: 203-929-8810
鈥?/div>
Fax: 203-926-9453
鈥?/div>
www.transwitch.com
鈥?/div>
USA
PRELIMINARY
information documents contain information on products in the
sampling, pre-production or early production phases of the product life cycle.
Characteristic data and other specifications are subject to change. Contact
TranSwitch Applications Engineering for current information on this product.
Proprietary TranSwitch Corporation Information for use Solely by its Customers

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