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Bit-serial SDH/SONET line interface
- Pseudo-ECL interface with clock recovery and synthesis
Byte-parallel SDH/SONET line interface
- Parity detection/generation with optional frame pulse input
Section, line, and path overhead byte processing
- RAM access for overhead bytes
- Line AIS, REI (FEBE) and RDI detection
- B2 and B3 byte BIP detection with BER measurement
- J0 byte TIM or single-byte comparison
- S1 byte change in synchronization status
- J1 byte TIM or 64-byte LF/CR alignment
- C2 byte PSL, unequipped, PDI detection
- G1 byte RDI (single-bit or three-bit), path REI (FEBE) detection
- H4 byte multiframe detection with optional V1 pulse generation
Section, line and path overhead byte insertion
- From RAM, interfaces, terminal, ring (mate device) or
receive side (e.g., RDI)
Supports 1+1 or 1:N APS applications
N1 byte tandem connection processing (STM-1 VC-4 format)
Interfaces
- TOH (RSOH & MSOH) bytes with programmable marker pulse
- K1/K2 APS bytes, E1 and E2 order wire bytes
- Section data communication (D1-D3) bytes
- Line data communication (D4-D12) bytes
- POH bytes (for VC-4 or each STS-1)
- Alarm Indication Port (AIP) for line/path ring operation
- Scan and drive leads (two each)
Telecom Bus terminal interface
- Clock, byte data, parity, C1J1V1, SPE, POH byte,
AIS indication, bus active indication
Tributary unequipped/AIS generation for TUG-3, TU-2/VT6, TU-12/VT2 and
TU-11/VT1.5
Telecom Bus terminal interface source timing mode
- Transmit timing for downstream devices from reference
clock and frame pulse
Receive and transmit pointer rejustification to receive and transmit reference clock
and frame pulse
Receive pointer tracking
- AIS, LOP, NDF and false pointer detection,
Receive and transmit line/path AIS generation
Motorola or Intel microprocessor interface for memory access
Boundary scan, loopbacks, and optional PRBS generator/detector
Single +3.3 volt, 鹵5% power supply; 5 volt tolerant inputs
256-lead, 27 mm x 27 mm, plastic ball grid array package
Device driver:
- Insulates application from register access details
- Driver APIs configure and manage the PHAST-3N device
- Default configurations are provided within the driver
- One command configures all the control registers
- Driver can download the firmware code into PHAST-3N
- Similar architecture to other device drivers, such as the TL3M
DESCRIPTION
The TranSwitch PHAST-3N (TXC-06103) is an STM-1/STS-3/ STS-
3c section, line and path overhead termination device that provides a
terminal side Telecom Bus interface. The PHAST-3N device provides
either a serial or parallel interface on the line side. The serial interface
provides 155 MHz clock recovery and clock synthesis. Line and
section overhead bytes are processed. The PHAST-3N performs
pointer tracking, and receive and transmit pointer justification. The
PHAST-3N also performs POH byte processing. TOH (RSOH and
MSOH) and POH bytes are written into RAM locations for
microprocessor access or provided via interfaces for external access. In
the transmit direction, the PHAST-3N will either interface to
downstream timing or provide the timing signals. The transmit POH
bytes can be inserted from RAM, a serial POH interface, a mate
PHAST-3N device for path and line ring applications, or directly from
the terminal side.
The PHAST-3N can generate line and path AIS in the receive and transmit
directions. For testing, the device provides boundary scan, a PRBS gen-
erator and analyzer, B2 and B3 byte BER measurements, programma-
ble BIP error mask generation, line and terminal loopback, and STS-1
terminal loopback. The device provides either Motorola or Intel micro-
processor access. Performance counters can be configured to be satu-
rating or roll-over. The interrupts, with mask bits, can be programmed
for activation on positive, negative, or positive and negative alarm tran-
sitions, or positive levels. A software polling register is also provided.
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APPLICATIONS
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Telecom Bus applications for TU/VT mappers
Line and path ring applications
Add/drop multiplexers
Cross connect systems
Data communications systems
LINE
SIDE
Boundary Scan
Clocks, Data,
and Control
Microprocessor
Interface
+3.3V
Receive
Reference
Clock and Frame
TERMINAL
SIDE
155.52 Mbit/s / 19.44 Mbyte/s
Bit-Serial / Byte-Parallel
Clock, Data, and Parity
PHAST-3N
STM-1/STS-3/STS-3c SDH/SONET
Overhead Terminator
with Telecom Bus Interface
Byte-Parallel
Telecom Bus
Signals
155.52 Mbit/s / 19.44 Mbyte/s
Bit-Serial / Byte-Parallel
Clock, Data, and Parity
Ring Port
Alarms
Transmit
Reference
Clock and Frame
Section / Line
Overhead Data,
Clock and Frame
Path
Overhead Data,
Clock and Frame
Section / Line
Datacom Data
and Clocks
U.S. Patents No. 4,967,405; 5,040,170; 5,141,529;
5,257,261, 5,265,096, 5,331,641, 5,724,362
U.S. and/or foreign patents issued or pending
Copyright
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2001 TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
TXC-06103-MC
Ed. 4, November 2001
TranSwitch Corporation
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3 Enterprise Drive
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Shelton, Connecticut 06484
Tel: 203-929-8810
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Fax: 203-926-9453
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www.transwitch.com
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USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
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