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TXC-04011-BIPQ Datasheet

  • TXC-04011-BIPQ

  • Telecomm/Datacomm

  • 60頁

  • ETC

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ADMA-T1P Device
1.544 Mbit/s to VT1.5/TU-11 Async Mapper-Desync
TXC-04011
DATA SHEET
Preliminary
FEATURES
鈥?Add/drop two 1.544 Mbit/s signals from an
STS-1, an STS-3/AU-3, or an STM-1 VC-4
鈥?Independent add and drop bus timing modes
鈥?Selectable AMI or B8ZS positive/negative rail or
NRZ T1 interface. Performance counter
provided for illegal coding violations
鈥?Digital desynchronizer reduces systemic jitter in
the presence of multiple pointer movements. A
register is also provided to control the internal
FIFO leak rate
鈥?Drop buses are monitored for parity, loss of
clock, and H4 multiframe errors
鈥?Performance counters are provided for VT/TU
pointer movements, BIP-2 errors and Far End
Block Errors (FEBEs)
鈥?VT/TUs are monitored for Loss Of Pointer, New
Data Flags (NDFs), AIS, Remote Defect
Indication (RDI), and size errors (S-bits)
鈥?V5 byte Signal Label Mismatch and Unequipped
detection
鈥?Loopback, generate BIP-2 errors, and send RDI
capability
鈥?Intel microprocessor interface
鈥?120-pin plastic quad 鏗俛t package
DESCRIPTION
The ADMA-T1P device is designed for add/drop
multiplexer, terminal multiplexer, and dual and single
unidirectional ring applications. Two T1 1.544 Mbit/s
signals are mapped to and from asynchronous 1.5
Virtual Tributaries (VT1.5s) or Tributary Unit - 11s (TU-
11s). The ADMA-T1P interfaces to a multiple-segment,
byte-parallel SONET/SDH-formatted bus at the 19.44
Mbit/s byte rate for STM-1/STS-3 operation or at the
6.48 Mbit/s byte rate for STS-1 operation. The T1 1.544
Mbit/s signals can be either AMI/B8ZS positive/negative
rail- or NRZ-formatted signals. The ADMA-T1P
provides performance counters, alarm detection, and
the ability to generate errors and Alarm Indication
Signals (AIS). T1 port loopback capability is also
provided. The dual timing mode Plus feature increases
the I/O signal pin count by 7 from the ADMA-T1 device
level so that the ADMA-T1P has a 120-pin package.
The ADMA-T1P bus interface is used to connect to
other TranSwitch devices such as the STM-1/STS-3/
STS-3c Overhead Terminator (SOT-3), TXC-03003, to
form an STS-3/STM-1 add/drop or terminal system.
鈥?STS-1/STS-3/STM-1 to 1.544 Mbit/s add/drop
mux/demux
鈥?Unidirectional or bidirectional ring applications
鈥?STS-1/STS-3/STM-1 termination terminal mode
multiplexer
鈥?STS-1/STS-3/STM-1 test equipment
PRELIMINARY
information documents contain information on products in the sampling, pre-production
or early production phases of the product life cycle. Characteristic data and other speci鏗乧ations are
subject to change. Contact TranSwitch Applications Engineering for current information on this product.
APPLICATIONS
STS-1/STS-3/STM - 1
LINE SIDE
A - side
drop bus
A - side
add bus
B - side
drop bus
B - side
add bus
+5V
12
13
12
13
1.544 Mbit/s
TERMINAL SIDE
ADMA-T1P
1.544 Mbit/s to VT1.5/TU-11
Async Mapper - Desync
TXC-04011
3
3
3
3
Port 1 receive
P, N, and clock
Port 1 transmit
P, N, and clock
Port 2 receive
P, N, and clock
Port 2 transmit
P, N, and clock
Microprocessor Timing Mode
interface
Select
U.S. Patents No.: 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057
U.S. and/or foreign patents issued or pending
Copyright
漏
1995 TranSwitch Corporation
TXC and TranSwitch are registered trademarks of TranSwitch Corporation
External
Clock
Document Number:
TXC-04011-MB
Ed. 1, September 1995
TranSwitch Corporation
鈥?/div>
8 Progress Drive
鈥?/div>
Shelton, CT 06484
鈥?/div>
USA
鈥?/div>
Tel: 203-929-8810
鈥?/div>
Fax: 203-926-9453

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