TL3M Device
Triple Level 3 Mapper
TXC-03453
PRODUCT INFORMATION
FEATURES
鈥?Maps up to three independent DS3/E3 line formats into SDH/
SONET formats as follows:
- DS3 to/from STM-1/TUG-3
- DS3 to/from STS-3/STS-1
- E3 to/from STM-1/TUG-3
鈥?SDH/SONET bus access:
- Byte-wide drop and Add buses
- Drop bus timing mode (Add bus timing derived from
Drop bus)
- Add bus timing mode (independent timing for
drop/Add buses)
鈥?Path overhead byte processing:
- Microprocessor access
- External interface
- B3 generation/detection with test mask
- B3 bit/block performance counters
- REI bit/block performance counters
- C2 mismatch detection
- C2 unequipped detection and generation
鈥?Alarm indication port
- Path REI count and RDI status for APS applications
鈥?O-bit channel access via external interface
鈥?Digital desynchronizer with internal pointer leak algorithm
鈥?Line interface:
- NRZ or P/N rail option for transmit and for receive
- Monitor NRZ transmit data
鈥?Microprocessor access:
- Motorola or Intel compatible
- Hardware interrupt with mask bits
- Software polling bits
鈥?Testing:
- Facility or line loopback
- PRBS generator/analyzer
- Boundary scan (IEEE 1149.1 standard)
鈥?A fully tested device driver is available
鈥?3.3 volt power supply, 5 volt tolerant inputs
鈥?324-lead plastic ball grid array package (23 mm x 23 mm)
DESCRIPTION
Each of the three channels of the TL3M can map a DS3 line signal
into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An
E3 signal can be mapped only into an STM-1 TUG-3. The TL3M
interfaces to an STM-1 or STS-3 SDH/SONET signal using a byte-
wide parallel interface in the TranSwitch Telecom Bus format. The
TL3M supports Drop bus and Add bus SDH/SONET timing modes.
Drop bus timing provides the timing signals for the add side. Timing
for both buses is independent for the Add bus timing mode. Individ-
ual POH bytes are mapped into a RAM interface for microprocessor
access and to an external interface for external processing if required.
In the add direction (except for the B3 byte) POH bytes may be
inserted individually from RAM locations, from the external inter-
face, or from the local side/alarm indication port. An option is pro-
vided to generate an unequipped channel or AIS. An external
interface is provided for accessing the O-bits. An alarm indication
port is provided for ring operation. The TL3M also uses internal dig-
ital desynchronizers that have a built-in pointer leak algorithm. The
line side can be configured for a NRZ or positive/negative rail inter-
face. For testing purposes, the TL3M provides boundary scan, PRBS
generators and analyzers, a BIP error mask, and DS3/E3 line and
facility loopbacks. The TL3M provides either Motorola or Intel
microprocessor access. The interrupt has programmable mask bits. A
software polling register is also provided.
APPLICATIONS
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鈥?/div>
鈥?/div>
鈥?/div>
Add/drop multiplexers
Digital cross connect systems
Broadband switching systems
Transmission equipment
SDH/SONET SIDE
(TELECOM BUS)
Drop Bus
O-Bit
Interfaces
External
Alarm
Interfaces
Control
Signals
POH
Interfaces
LINE SIDE
TL3M
Triple Level 3 Mapper
TXC-03453
Receive Interfaces (3)
(Rail, NRZ)
Transmit Monitor
Interfaces (3)
Transmit Interfaces (3)
(Rail, NRZ)
Add Bus
Microprocessor
Interface
Alarm
Indication
Port
Boundary
Scan
U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096
U.S. and/or foreign patents issued or pending
Copyright 漏 2001 TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
TXC-03453-MC
Ed. 4, December 2001
TranSwitch Corporation
鈥?/div>
3 Enterprise Drive
鈥?/div>
Shelton, Connecticut 06484
Tel: 203-929-8810
鈥?/div>
Fax: 203-926-9453
鈥?/div>
www.transwitch.com
鈥?/div>
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
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