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TXC-03452CIOG Datasheet

  • TXC-03452CIOG

  • Telecommunication IC

  • 1023.33KB

  • 96頁(yè)

  • ETC

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L3M Device
Level 3 Mapper
TXC-03452B
DATA SHEET
FEATURES
鈥?Maps DS3 (44.736 Mbit/s) or E3 (34.368 Mbit/s) line
formats into SDH/SONET formats as follows:
- DS3 to/from STM-1/TUG-3
- DS3 to/from STS-3/STS-1 SPE or STS-1 SPE
- E3 to/from STM-1/TUG-3 only
鈥?SDH/SONET bus access:
- Drop/add data byte access (with clock, C1J1, SPE,
and parity)
- Add bus interface timing derived from drop bus, add
bus, or external timing
鈥?Path overhead byte processing:
- Microprocessor or external interface
- B3 generation and detection with test mask
- B3 performance counter (16-bit) and block error
counter (8-bit)
- C2 mismatch and unequipped detection
- G1 processing
- FEBE count by block or bits (16-bit counter)
鈥?Microprocessor access:
- Motorola or Intel compatible (selected via a lead)
- Hardware/software interrupt capability
鈥?Line Interface
- Transmit and receive NRZ or rail operation with split
operation capability
鈥?Testing functions:
- SONET, facility, or line loopback
- Transmit and receive 2
15
-1 or 2
23
-1 generators and
shared analyzer
- Boundary scan capability (IEEE 1149.1)
鈥?144-lead plastic quad flat package (PQFP) or
208-lead plastic ball grid array package (PBGA)
DESCRIPTION
The L3M maps a DS3 line signal into an STM-1 TUG-3 or STS-3/
STS-1 SPE or STS-1 SPE SDH/SONET signal. An E3 line signal
is mapped into an STM-1 TUG-3 signal only. The L3M provides a
TUG-3 formatted signal for STM-1 operation, or an STS SPE for
STS-3 or STS-1 operation. The SDH/SONET signal is transmitted
via an add bus with timing derived from the drop side, add side or
from external timing (STS-1 only). An option is provided to gener-
ate the A1, A2 framing pattern, C1 byte and H1, H2 pointer
towards the add bus when external timing mode is selected.
APPLICATIONS
鈥?Add/drop multiplexers
鈥?Digital cross-connect systems
鈥?Broadband switching systems
鈥?Transmission equipment
SDH/SONET SIDE
鈥淥鈥?Bits
I/O
Ext
Alarms
Control
Microprocessor
Interface
LINE SIDE
Add Bus
L3M
Level 3 Mapper
NRZ, Rail Input
NRZ Clock,
Data (Monitor)
NRZ, Rail Output
Drop Bus
TXC-03452B
POH
I/O
VCXO Boundary Alarm
Port I/O
Scan
Document Number:
TXC-03452B-MB
Ed. 6, April 2001
U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096
U.S. and/or foreign patents issued or pending
Copyright
餂?/div>
2001 TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
TranSwitch Corporation
鈥?/div>
3 Enterprise Drive
鈥?/div>
Shelton, Connecticut 06484
Tel: 203-929-8810
鈥?/div>
Fax: 203-926-9453
鈥?/div>
www.transwitch.com
鈥?/div>
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Individual POH bytes for the transmitted SDH/SONET signal
are mapped from the L3M memory map or an external inter-
face. An option is provided to generate an unequipped status
or TUG-3 path AIS signal. External accesses are provided for
the communications channel 鈥淥鈥?bits and alarms for ring oper-
ation. The received signal is desynchronized from drop bus
STM-1/TUG-3, STS-3/STS-1 SPE, or STS-1 signals. Internal
pointer processing is performed for the TUG-3 signal. All POH
bytes are provided for the microprocessor.

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