鈥?/div>
USB On-the-Go (OTG) Controller Core
鈥?Use Mentor Graphics USB 2.0 OTG Core
鈥?Dual-Role Controller Can Operate Either as
a Function Controller for a USB Peripheral
or as the Host/Peripheral in Point-to-Point
or Multi-Point Communications With Other
USB Functions
鈥?Compliant With the USB 2.0 Standard for
High-Speed (480-Mbps) Functions and
With the OTG Supplement to the USB 2.0
Specification
鈥?Supports OTG Communications With One
or More High-, Full-, or Low-Speed Devices
鈥?Supports Session Request Protocol (SRP)
and Host Negotiation Protocol (HNP)
鈥?Supports Suspend-and-Resume Signaling
鈥?Configurable for up to 15 Transmit
Endpoints and up to 15 Receive Endpoints
鈥?Configurable FIFOs, Including the Option
of Dynamic FIFO Sizing
鈥?16k-Byte RAM for USB Endpoint FIFO
Shared by USB In/Out Endpoints
鈥?Support for External Direct Memory
Access (DMA) to FIFOs
鈥?Soft Connect/Disconnect Option
鈥?Performs All Transaction Scheduling in
Hardware
Integrated USB 2.0 OTG PHY
鈥?Fully Compliant With USB 2.0 Standard
and USB 2.0 Transceiver Macrocell
Interface (UTMI) Revision 1.05
鈥?Optimized One-Port Operation at Low
Speed (1.5 Mbps), Full Speed (12 Mbps),
and High Speed (480 Mbps)
鈥?Support for External Charge Pump
鈥?Supports UTMI+3 Level 3 (Host and OTG
Devices, High/Full/Low Speed and
Preamble Packet)
鈥?Protection Circuitry to Withstand Possible
VBUS Short
鈥?Use 19.200-MHz, 24.000-MHz, or
48.000-MHz Reference Clock Input as a
Crystal or External Clock Driver
鈥?At-Speed Built-In Self Test (BIST) With
Internal Asynchronous Capability Through
Loopback
鈥?On-Chip Integrated Accurate 45-鈩?/div>
High-Speed Termination, 1.5-k鈩?Pullup,
and 15-k鈩?Pulldown Resistors
鈥?On-Chip Phase-Locked Loop (PLL) to
Reduce Noise on the High-Speed Clocks
鈥?Active Power Consumption Less Than
100 mW
VLYNQ 2.0 Interface to External Host
Controller
鈥?High-Speed (150-MHz) Point-to-Point Serial
Interface for Direct Connection to Other
VLYNQ Interface
鈥?Supports 4X RX and 4X TX Lines
鈥?Memory-Mapped Master/Slave
鈥?Hardware Flow Control Internal Loopback
Mode
鈥?Multichannel DMA Controller
鈥?Integrated List Processor Capable of
Parsing Communications Port
Programming Interface (CPPI)
3.0-Compliant Buffer Descriptors
System Control Module
鈥?Controls Clock and Reset Generation and
Distribution
鈥?Controls and Observes Device Power
States
鈥?Controls Test and Debug Modes
鈥?Supports External Power Management
V
BUS
Switched Central Resource
鈥?Supports Two VBUSP Master and Three
VBUSP Slave Interfaces
High-Performance 80-Pin
MicroStar BGA鈩?MicroStar Junior鈩?/div>
ZQE Package
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar BGA, MicroStar Junior, MicroStar BGA are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright 漏 2007, Texas Instruments Incorporated
PRODUCT PREVIEW
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