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TSS461CD Datasheet

  • TSS461CD

  • LAN Node Controller

  • 52頁

  • ETC

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TSS461C
Vehicle Area Network Data Link Controller
1. Description
Cost optimization in car manufacturing is of extreme importance today. Solutions to this problem often implies the
use of more advanced and intelligent electronic circuits.
The TSS461C is such a circuit, which allows the transfer of all the status information needed in a car or truck over a
single low-cost wire pair, thereby minimizing the electrical wire usage.
It can be used to interconnect powerful functions (ABS, dashboard, power train control) and to control and interface
car body electronics (lights, wipers, power window...).
The TSS461C is fully compliant with the ISO standard ISO/11519-3. This standard supports a wide range of
applications such as low-cost remote controlled switches, typically used for lamp control, up to complex, highly
autonomous, distributed systems like engine controls, which require fast and secure data transfers.
The TSS461C is a microprocessor interfaced line controller for mid to high complexity bus-masters and listeners like
injection/ignition control calculators, dashboard controllers and car stereo or mobile telephone CPUs.
The microprocessor interface consists of a 256 byte RAM and register area divided into 11 control registers, 14 channel
register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in the RAM using DMA techniques, controlled by the channel and control registers. This allows
virtually any microprocessor to interface with ease to the TSS461C, and to use the free RAM as a scratch pad.
Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link,
at a maximum bit rate of 1 Mbit/s. The TSS461C analyzes the messages received or transmitted according to 6 different
criterias including some higher level checks.
In addition the bus interface has three separate inputs with automatic source diagnosis and selection, allowing for
multibus listening or the automatic selection of the most reliable source at any time if several line receivers are
connected to the same bus.
2. Features
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Fully compliant to VAN specification ISO/11519.3.
Handles all specified module types.
Handles all specified message types.
Handles retransmission of frames on contention and errors.
3 separate line inputs with automatic diagnosis and selection.
1 Mbit/s maximum transfer rate.
Normal or pulsed (optical and radio mode) coding.
INTEL, NEC, TI and MOTOROLA compatible 8-bit microprocessor interface.
Multiplexed address and data bus.
Idle and sleep modes.
128 bytes of general purpose RAM.
DMA capabilities for message handling.
14 identifier registers with all bits individually maskable.
6-source maskable interrupt including an interrupt-on-reset to detect glitches on the reset pin.
Integrated crystal or resonator oscillator with internal baud rate generator and buffered clock output.
Single +5V power supply.
0.8
碌m
CMOS technology.
SOP 24 packaging.
Rev. D (22 Feb 01)
1

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