Product Brief
February 2002
TSRD1003G
~1.06鈥?.2 Gbits/s Serializer and Deserializer (Macro)
Features
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Potential Applications
Drives chip-to-chip and across backplanes.
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Designed to operate in Ethernet, fibre channel,
InfiniBand
鈩? and SONET/SDH (synchronous digi-
tal hierarchy) applications.
Selectable data rate (1.06 Gbits/s鈥?.2 Gbits/s).
100 MHz鈥?68 MHz reference clock frequency
range.
16-bit or 20-bit parallel I/O interface in full-rate
mode.
Programmable control and configuration interface
to define the various device configurations.
Analog modularity and digital library interface for
design flexibility.
Automatic lock-to-reference in absence of receive
data.
CML high-speed interface I/O for use with back-
plane or cable media.
Programmable transmit pre-emphasis optimized
for backplane applications.
SONET
Fibre Channel
InifiniBand
10 Gbit Ethernet (XAUI)
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Description
The TSRD1003G is a high-speed serializer/deserial-
izer (SERDES) macrocell. This macro cell includes a
current mode logic (CML) high-speed serial interface
and makes use of a proprietary CDR architecture
along with the sharing of a PLL across multiple RX
and TX channels to reduce area and power con-
sumption. These characteristics make it suitable for
applications that require high channel counts.
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CDR
Requires one external resistor for bias current gen-
eration.
Requires no external components for clock recov-
ery and frequency synthesis.
105 mW per transceiver (typical).
Low powerdown dissipation.
DIN
DEMUX
D19
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R
X
D0
CKOUT
PARALLEL
LOOPBACK
D19
DO
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1.5 V 鹵 5% power supply.
1.8 V 鹵 5% power supply option for differential
high-speed I/O circuits.
0 擄C鈥?25 擄C junction temperature.
DOUT
SERIAL
LOOPBACK
Half amplitude mode for reduced power consump-
tion in chip-to-chip applications.
REFCLK
PLL
DIGITAL
LIBRARY
INTERFACE
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MUX
DIV
T
X
SERIAL
INTERFACE
Figure 1. TSRD1003G for COM2/2H
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