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TSC695F Datasheet

  • TSC695F

  • TSC695F [Updated 6/03. 42 Pages]

  • 42頁

  • ETC

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F
eatures
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Integer Unit Based on SPARC V7 High-performance RISC Architecture
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Optimized Integrated 32/64-bit Floating-point Unit
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On-chip Peripherals
鈥?EDAC and Parity Generator and Checker
鈥?Memory Interface
Chip Select Generator
Waitstate Generation
Memory Protection
鈥?DMA Arbiter
鈥?Timers
General Purpose Timer (GPT)
Real-time Clock Timer (RTCT)
Watchdog Timer (WDT)
鈥?Interrupt Controller with 5 External Inputs
鈥?General Purpose Interface (GPI)
鈥?Dual UART
Speed Optimized Code RAM Interface
8- or 40-bit boot-PROM (Flash) Interface
IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
Fully Static Design
Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz
Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs
Operating Range: 4.5V to 5.5V
(1)
-55擄C to +125擄C
Total Dose Radiation Capability (Parametric and Functional): 300 KRADs (Si)
SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)
Latch-up Immunity Better than (LET) 100 MeV-cm
2
/mg
Quality Grades: ESA SCC, QML Q or V
Package: 256 MQFPF; Bare Die
1. For 3.3V capability see the TSC695FL datasheet on the Atmel site.
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Rad-Hard 32-bit
SPARC
Embedded
Processor
TSC695F
Note:
Description
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit
RISC embedded processor implementing the SPARC architecture V7 specification. It
has been developed with the support of the ESA (European Space Agency), and
offers a full development environment for embedded space applications.
The processor is manufactured using the Atmel 0.5 碌m radiation tolerant (
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300
KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for
space, as it has on-chip concurrent transient and permanent error detection.
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a
Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers
a high security watchdog, two timers, an interrupt controller, parallel and serial inter-
faces. Fault tolerance is supported using parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.
Rev. 4118H鈥揂ERO鈥?6/03

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