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and the IEEE 1394a-2000
Supplement
Fully Interoperable With FireWire鈩?and
i.LINK鈩?Implementation of IEEE Std 1394
Meets Intel鈩?Mobile Power Guideline 2000
Full IEEE 1394a-2000 Support Includes:
Connection Debounce, Arbitrated Short
Reset, Multispeed Concatenation,
Arbitration Acceleration, Fly-By
Concatenation, Port Disable/Suspend/
Resume
Power-Down Features to Conserve Energy
In Battery-Powered Applications Include:
Automatic Device Power Down During
Suspend, PCI Power Management for
Link-Layer, and Inactive Ports Powered
Down
Ultralow-Power Sleep Mode
Provides Two IEEE 1394a-2000 Fully
Compliant Cable Ports at 100/200/400
Megabits Per Second (Mbits/s)
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
Cable Power Presence Monitoring
Separate Cable Bias (TPBIAS) for Each Port
3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments
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Physical Write Posting of up to Three
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Outstanding Transactions
Implements PCI Burst Transfers and Deep
FIFOs to Tolerate Large Host Latency
Supports PCI-CLKRUN Protocol
External Cycle Timer Control for
Customized Synchronization
Extended Resume Signaling for
Compatibility With Legacy DV Components
PHY-Link Logic Performs System
Initialization and Arbitration Functions
PHY-Link Encode and Decode Functions
Included for Data-Strobe Bit Level
Encoding
PHY-Link Incoming Data Resynchronized to
Local Clock
Low-Cost 24.576-MHz Crystal Provides
Transmit and Receive Data at 100/200/400
Mbits/s
Node Power Class Information Signaling
for System Power Management
Serial ROM Interface Supports Two-Wire
Devices
Provides Two General-Purpose I/Os
Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit and IEEE 1394a-2000
Features
Fabricated in Advanced Low-Power CMOS
Process
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description
The Texas Instruments TSB43AA22 is an integrated PHY/link device that is fully compliant with
PCI Local Bus (Rev.
2.2), PCI Bus Power Management Interface (Rev. 1.1),
IEEE 1394-1995, IEEE 1394a-2000, and
1394 Open Host
Controller Interface Specification (Rev. 1.0).
It is capable of transferring data between the 33-MHz PCI bus and 1394
bus at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB43AA22 provides two 1394 ports which have separate
cable bias (TPBIAS). The TSB43AA22 also supports IEEE 1394a-2000 power-down features for battery-operated
applications and arbitration enhancements.
The TSB43AA22 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at
132 Mbytes/s after connection to the memory controller. Since PCI latency can be large even on PCI Revision 2.2
systems, deep FIFOs are provided to buffer the 1394 data.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Inc.
Intel is a trademark of Intel Corporation.
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation
鈥營(yíng)mplements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright
漏
2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
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