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TSB41LV01PAP Datasheet

  • TSB41LV01PAP

  • IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

  • 615.31KB

  • 49頁(yè)

  • TI

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TSB41LV01
IEEE 1394A ONE-PORT CABLE
TRANSCEIVER/ARBITER
SLLS365 鈥?AUGUST 1999
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Fully Supports Provisions of IEEE
1394-1995 Standard for High Performance
Serial Bus
鈥?/div>
and the P1394a Supplement
Fully Interoperable With FireWire鈩?and
i.LINK鈩?Implementation of IEEE Std 1394
Fully Compliant With OpenHCI
Requirements
Provides One P1394a Fully Compliant
Cable Port at 100/200/400 Megabits per
Second (Mbits/s)
Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-by Concatenation, Port
Disable/Suspend/Resume
Extended Resume Signaling for
Compatibility With Legacy DV Devices
Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Pin, Link
Interface Disable via LPS, and Inactive Port
Powered-Down
Ultra Low-Power Sleep Mode
Node Power Class Information Signaling
for System Power Management
Cable Power Presence Monitoring
Cable Port Monitors Line Conditions for
Active Connection to Remote Node
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Register Bits Give Software Control of
Contender Bit, Power Class bits, Link
Active Control Bit and P1394a Features
Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
Interface to Link Layer Controller Supports
Low Cost TI鈩?Bus-Holder Isolation and
Optional Annex J Electrical Isolation
Interoperable With Link-Layer Controllers
Using 3.3 V and 5 V Supplies
Interoperable With Other Physical Layers
(Phys) Using 3.3 V and 5 V Supplies
Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
Incoming Data Resynchronized to Local
Clock
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
Single 3.3 Volt Supply Operation
Meets Intel Mobile Power Guideline 2000
Low Cost High Performance 64 Pin TQFP
(PAP) Thermally Enhanced Package
description
The TSB41LV01 provides the digital and analog transceiver functions needed to implement a two-port node in
a cable-based IEEE 1394 network. The cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV01 is designed to interface
with a link layer controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV23, TSB12LV31, TSB12LV41,
TSB12LV42 or TSB12LV01A.
The TSB41LV01 requires only an external 24.576 MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock
signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Incorporated.
i.LINK is a trademark of SONY.
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
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1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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