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TSB41BA3-EP Datasheet

  • TSB41BA3-EP

  • Military Enhanced Plastic IEEE 1394b Three-Port Cable Transc...

  • 791.48KB

  • 62頁

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TSB41BA3-EP
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SGLS173 鈥?JUNE 2003
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Controlled Baseline
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鈥?One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
鈥?0擄C to 110擄C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
鈥?/div>
Fully Supports Provisions of IEEE
1394b-2002 at S100, S100B, S200, S200B,
S400, and S400B Signaling Rates (B
Signifies 1394b Signaling)
Fully Supports Provisions of IEEE
1394a-2000 and 1394-1995 Standards for
High Performance Serial Bus
Fully Interoperable With Firewire錚?
SB1394錚? DishWire錚? and i.LINK錚?/div>
Implementation of IEEE Std 1394
Provides Three Fully Backward
Compatible, (1394a-2000 Fully Compliant)
Bilingual 1394b Cable Ports at
400 Megabits per Second (Mbits/s)
Same Three Fully Backward Compatible
Ports Are 1394a-2000 Fully Compliant
Cable Ports at 100/200/400 Mbits/s
Full 1394a-2000 Support Includes:
鈥?Connection Debounce
鈥?Arbitrated Short Reset
鈥?Multispeed Concatenation
鈥?Arbitration Acceleration
鈥?Fly-By Concatenation
鈥?Port Disable/Suspend/Resume
鈥?Extended Resume Signaling for
Compatibility With Legacy DV Devices
Power-Down Features to Conserve Energy
in Battery Powered Applications
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Low-Power Sleep Mode
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Automotive Sleep Mode Support
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Fully Compliant With Open Host Controller
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Interface (HCI) Requirements
Cable Power Presence Monitoring
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit, and 1394a-2000
Features
Data Interface to Link-Layer Controller Pin
Selectable From 1394a-2000 Mode (2/4/8
Parallel Bits at 49.152 MHz) or 1394b Mode
(8 Parallel Bits at 98.304 MHz)
Interface to Link-Layer Controller Supports
Low Cost TI Bus-Holder Isolation
Interoperable With Link-Layer Controllers
Using 3.3-V Supplies
Interoperable With Other 1394 Physical
Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V
Supplies
Low Cost 49.152-MHz Crystal Provides
Transmit and Receive Data at
100/200/400 Mbits/s, and Link-Layer
Controller Clock at 49.152 MHz and
98.304 MHz
Separate Bias (TPBIAS) for Each Port
Low Cost, High Performance 80-Pin TQFP
(PFP) Thermally Enhanced Package
Software Device Reset (SWR)
Fail-Safe Circuitry Senses Sudden Loss of
Power to the Device and Disables the Ports
to Ensure That the TSB41BA3 Does Not
Load the TPBIAS of Any Connected Device
and Blocks Any Leakage From the Port
Back to Power Plane
The TSB41BA3 Has a 1394a-2000
Compliant Common-Mode Noise Filter on
the Incoming Bias Detect Circuit to Filter
Out Cross-Talk Noise
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鈥?Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation.
FireWire is a trademark of Apple Computer Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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