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TSB41AB2 Datasheet

  • TSB41AB2

  • IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER

  • 49頁

  • TI

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TSB41AB2, TSB41AB2I
IEEE 1394a 2000 TWO PORT CABLE
TRANSCEIVER/ARBITER
SLLS424F 鈭?JUNE 2000 鈭?REVISED MARCH 2004
D
Fully Supports Provisions of IEEE
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1394-1995 Standard for High Performance
Serial Bus
鈥?/div>
and IEEE 1394a-2000
Fully Interoperable With FireWire錚?and
i.LINK錚?Implementation of IEEE Std 1394
Fully Compliant With OpenHCI
Requirements
Provides Two IEEE 1394a-2000 Fully
Compliant Cable Ports at 100/200/400
Megabits Per Second (Mbits/s)
Full IEEE 1394a-2000 Support Includes:
Connection Debounce, Arbitrated Short
Reset, Multispeed Concatenation,
Arbitration Acceleration, Fly-By
Concatenation, Port
Disable/Suspend/Resume
Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit and IEEE 1394a-2000
Features
IEEE 1394a-2000 Compliant Common Mode
Noise Filter on Incoming TPBIAS
Extended Resume Signaling for
Compatibility With Legacy DV Devices, and
Terminal- and Register-Compatibility With
TSB41LV02A, Allow Direct Isochronous
Transmit to Legacy DV Devices With Any
Link Layer Even When Root
Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power Down During
Suspend, Device Power-Down Terminal,
Link Interface Disable via LPS, and Inactive
Ports Powered Down
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Fail-Safe Circuitry Senses Sudden Loss of
Power to the Device and Disables the Port
to Ensure That the Device Does Not Load
TPBIAS of the Connected Device and
Blocks Any Leakage Path From the Port
Back to the Device Power Plane
Software Device Reset (SWR)
Industry Leading Low Power Consumption
Ultralow-Power Sleep Mode
Cable Power Presence Monitoring
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
Data Interface to Link Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
Interface to Link Layer Controller Supports
Low-Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation
Interoperable With Link Layer Controllers
Using 3.3 V
Single 3.3-V Supply Operation
Low-Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
Low-Cost High-Performance 64-Pin TQFP
Thermally Enhanced PowerPAD錚?Package
Increases Thermal Performance by up to
210%
Meets Intel錚?Mobile Power Guideline 2000
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
鈥營mplements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.
Intel is a trademark of Intel Corporation
Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2003 鈭?2004 Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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