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TS88915T Datasheet

  • TS88915T

  • TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Dr...

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Features
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Vcc = 5V 鹵 5%
Military Temperature Range
Fully Compatible with the TS68040
Five Low Skew Outputs
鈥?Five Outputs (Q0-Q4) with Output-to-Output Skew < 500 ps Each Being Phase End
Frequency Locked to the SYNC Input
Three Additional Outputs are Available:
鈥?The 2X_Q Output Runs Twice the System 鈥淨(jìng)鈥?Frequency
鈥?The Q/2 Output Runs At 1/2 the System 鈥淨(jìng)鈥?Frequency
鈥?The Q5 Output is Inverted (180擄 Phase Shift)
Two Selectable Clock Inputs
鈥?Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes
鈥?Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
鈥?All Outputs Can Go Into High Impedance (3-state) for Board Test Purposes
Input Frequency Range From 5 MHz to 2X_Q FMAX
Three Input/Output Ratios
鈥?Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available
Low Part-to-part Skew
鈥?The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is
Less than 550 ps (Derived From the tPD Specification, which Defines the
Part-to-part Skew)
CMOS and TTL Compatible
鈥?All Outputs Can Drive Either CMOS or TTL Inputs
鈥?All Inputs are TTL-level Compatible
LOCK Indicator (LOCK) Indicates a Phase-locked State
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Low Skew
CMOS PLL
Clock Driver
Tri-State 70 and
100 MHz
Versions
TS88915T
Description
The TS88915T Clock Driver utilizes a phazed-locked loop (PLL) technology to lock its
low skew outputs鈥?frequency and phase onto an input reference clock. It is designed to
provide clock distribution for high performance microprocessors such as TS68040,
TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM鈥檚, MMU鈥檚.
Screening/Quality
This Product is Manufactured:
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Based Upon the Generic Flow of MIL-STD-883
or According to Atmel-Grenoble Standard
R suffix
PGA 29
Ceramic Pin Grid Array
W suffix
LDCC 28
Leaded Ceramic Chip Carrier
Rev. 2122A鈥揌IREL鈥?6/02
1

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