Errata Sheet
TS80C51U2/TS87C51U2/TS83C51U2
This errata sheet describes the functional deviations known at the release date of this document.
Errata History
TS87C51U2
Lot Number
Trouble list
Status
All
T01, T02, T03, T04, T05, T06, T08, T09
Not Fixed
TS80C51U2-TS83C51U2
Lot Number
Trouble list
Status
All
T01, T02, T03, T04, T05, T06, T07, T08, T09
Not Fixed
Trouble descriptions
T01
Description:
Workaround:
Baud Rate Generator clock
In idle mode, the baud rate generator clock is off
Use Timer1 or Timer 2 to generate baud rate when idle mode is required.
T02
Description:
Workaround:
Port/level/read at 0 after reset vs External pull-down
After Reset, if the External pull-down connected to the port is too low, the Port is read at 0 level.
The external pull-down connected during Reset must be larger than (90Kohm if Medium pull-
up=300Kohm @Vcc=5V)
T03
Description:
Workaround:
UART / Reception in modes 1, 2 and 3 / UART false start bits detection
When a false start bit occurs on the UART, some UART internal signals are not reset. Than
when a real start bit occurs, the sampling is shifted.
No
T04
Description:
Workaround:
During UART reception, clearing REN may generate unexpected IT.
During UART reception, if the REN bit is clear between a start bit detection and the end of
reception, the UART will not discard the data (RI is set).
Test REN at the beginning of Interrupt routine just after CLR RI, and to run the Interrupt routine
code only if REN is set.
T05
Description:
Workaround:
JBC / Double IT when external Interrupt occurs during JBC instruction
On polling algorithm in ISR on IE1 or IE0 bit, when external IT appears during JBC instruction
, flag is not cleared and next JBC sees another IT, then the same IT is seen twice.
Use JB Instruction instead of JBC instruction to test bit and CLR instruction to clear it.
Rev. A - 29-Mar-01
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