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TS8308500CG Datasheet

  • TS8308500CG

  • A/D CONVERTER

  • 42頁

  • ETC

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MAIN FEATURES
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8-bit resolution.
500 Msps (min) sampling rate.
1.3 GHz full power input bandwidth.
Band Flatness:
TBD
Input VSWR (packaged device):
TBD
SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
@ F
S
= 500 Msps, F
IN
= 20 MHz :
SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc
@ F
S
= 500 Msps, F
IN
= 250 MHz :
SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc
@ F
S
= 500 Msps, F
IN
= 500 MHz (-3 dB FS)
2-tone IMD :
TBD
(199.5 MHz, 200.5 MHz) @ 500 MSPS.
DNL =
鹵
0.3 LSB
INL =
鹵
0.7 LSB.
Low Bit Error Rate (10
-13
) @ 500 Msps, Tj = 90擄C
Power consumption : 3.8 W @ Tj = 70擄C Typical
500 mVpp differential or single-ended analog inputs.
Differential or single-ended 50鈩?ECL compatible clock inputs.
ECL or LVDS/HSTL output compatibility.
ADC gain adjust.
Data ready output with asynchronous reset.
Gray or Binary selectable output data ; NRZ output mode.
ADC 8-bit 500 Msps
TS8308500
APPLICATIONS
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Digital Sampling Oscilloscopes.
Satellite receiver.
Electronic countermeasures / Electronic warfare.
Direct RF down鈥揷onversion.
SCREENING
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Atmel-Grenoble standard screening level
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Temperature range: up to 0擄C < Tc ; Tj < +90擄C
1/ Evaluation board :
TSEV8308500
Detailed specification on request.
2/ Demultiplexer : parallel 8-bit 2 Gsps
TS81102G0 : companion device available
DESCRIPTION
The TS8308500 is a monolithic 8鈥揵it analog鈥搕o鈥揹igital converter, designed for
digitizing wide bandwidth analog signals at very high sampling rates of up to 500
Msps.
The TS8308500 is using an innovative architecture, including an on chip Sample
and Hold (S/H), and is fabricated with an advanced high speed bipolar process.
The on鈥揷hip S/H has a 1.3 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
G Suffix : CBGA 72
Ceramic Ball Grid Array
With decoupling R and C on the package
January 2002
Product Specification
尾
-site

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