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TS81102G0FS Datasheet

  • TS81102G0FS

  • TS81102G0FS Summary [Updated 9/03. 10 Pages] DMUX 8/10 bit. ...

  • 10頁

  • ETC

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Main Features
鈥?/div>
Programmable DMUX Ratio:
鈥?1:4 Data Rate Max = 1 Gsps
鈥?P
D
(8b/10b) < 4.3/4.7 W (ECL 50
鈩?/div>
Output)
鈥?1:8 Data Rate Max = 2 Gsps
鈥?P
D
(8b/10b) < 6/6.9 W (ECL 50
鈩?/div>
Output)
鈥?1:16 With 1 TS8388B or 1 TS83102G0 and 2 DMUX
Parallel Output Mode
8/10-bit
ECL Differential Input Data
Data Ready or Data Ready 2 Input Clock
Input Clock Sampling Delay Adjust
Single-ended Output Data:
鈥?Adjustable Common Mode and Swing
鈥?Logic Threshold Reference Output
鈥?ECL, PECL, TTL
Asynchronous Reset
Synchronous Reset
ADC and DMUX Multi-channel Applications:
鈥?Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment
Differential Data Ready Output
Built-in Self Test (BIST)
Dual Power Supply V
EE
= -5 V, V
CC
= 5 V
Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected)
Thermally Enhanced CQFP196 Cavity Up Package
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1:4/1:8 8/10-bit
2 Gsps
DMUX
TS81102G0FS
Target
Specification
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Screening
鈥?/div>
Temperature Range:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
C Grade: 0擄C < Tc; Tj < 90擄C
V Grade: -40擄C < Tc; Tj < 110擄C
M Grade: -55擄C < Tc; Tj < 125擄C
For more information please
contact
hotline-bdc@gfo.atmel.com
Summary
Standard Screening Level for 鈥淐鈥? 鈥淰鈥?and 鈥淢鈥?Grades
ESA SCC 9000 Space Screening Flow for 鈥淢鈥?Grade (on Request)
For commercial and industrial temperature ranges the DMUX is also available in a
TBGA240 package (P/N: TS81102G0CTP and TS81102G0VTP).
Note:
Description
The TS81102G0 is a monolithic 10-bit high-speed (up to 2 Gsps) demultiplexer.
The DMUX is designed to run with all kinds of ADCs and more specifically, it fits per-
fectly with Atmel鈥檚 high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps
TS83102G0B. The TS81102G0 uses an innovative architecture, including a sampling
delay adjust and tunable output levels. This DMUX allows users to process the high-
speed output data stream down to standard signal processors speed (standard
FPGAs).
5344AS鈥揃DC鈥?9/03
Note: This is a summary document. A complete document is not available
at this time. For more information, please contact your local Atmel sales
office.
1

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