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TS81102G0CTP Datasheet

  • TS81102G0CTP

  • DMUX 8-/10-bit 2 GHz 1:4/8

  • 38頁(yè)

  • ATMEL   ATMEL

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Features
鈥?/div>
Programmable DMUX Ratio:
鈥?1:4: Data Rate Max = 1 Gsps
鈥?PD (8b/10b) < 4.3/4.7 W (ECL 50鈩?output)
鈥?1:8: Data Rate Max = 2 Gsps
鈥?PD (8b/10b) < 6/6.9 W (ECL 50鈩?output)
鈥?1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX
Parallel Output Mode
8-/10-bit
ECL Differential Input Data
DataReady or DataReady/2 Input Clock
Input Clock Sampling Delay Adjust
Single-ended Output Data:
鈥?Adjustable Common Mode and Swing
鈥?Logic Threshold Reference Output
鈥?(ECL, PECL, TTL)
Asynchronous Reset
Synchronous Reset
ADC + DMUX Multi-channel Applications:
鈥?Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment
Differential Data Ready Output
Built-in Self Test (BIST)
Dual Power Supply V
EE
= -5V, V
CC
= +5V
Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected)
TBGA 240 (Cavity Down) Package
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DMUX 8-/10-bit
2 GHz 1:4/8
TS81102G0
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Description
The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor,
designed to run with all kinds of ADCs and more specifically with Atmel鈥檚 high-speed
ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B.
The TS81102G0 uses an innovative architecture, including a sampling delay adjust
and tunable output levels. It allows users to process the high-speed output data
stream down to processor speed and uses the very high-speed bipolar technology (25
GHz NPN cut-off frequency).
Rev. 2105C鈥揃DC鈥?1/03
1

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