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Z38711
> Z38711
T01, T02 ,T03, T04, T05, T06
T02 ,T03, T04, T05, T06
Not Fixed
Not Fixed
Trouble descriptions
T01
Description:
Workaround:
UART / Reception in modes 1, 2 and 3 / UART false start bits detection
When a false start bit occurs on the UART, some UART internal signals are not reset. Than
when a real start bit occurs, the sampling is shifted.
No
T02
Description:
Workaround:
During UART reception, clearing REN may generate unexpected IT
During Uart reception, if the REN bit is clear between a start bit detection and the end of
reception, the Uart will not discare the data (RI is set).
Test REN at the beginning of Interrupt routine just after CLR RI, and to run the Interrupt routine
code only if REN is set.
T03
Description:
Workaround:
JBC / Double IT when ext. IT occurs during JBC instruction
On polling algorithm in ISR on IE1 or IE0, when external IT appears during JBC instruction ,
flag is not cleared and next JBC see another IT, then the same IT is seen twice.
Use JB Instruction instead of JBC instruction to test bit and CLR instruction to clear it.n twice.
T04
Description:
Timer2 / Downcounter mode / Double IT with slow external clock
Double IT with slow external clock in downcount mode.Timer 2 in 16 bit autoreload in count
down mode with external clock input 2 interrupts are generated successively with low frequency
on clock input (typ 10-40KHz).
Reload FFFE into TH2-TL2 in ISR and count down to RCAP-1 (to recover cycle lost in ISR)
Caution : do not work if initially RCAP = 0x0000
Workaround:
Rev A - 29-Mar-01
1
1
2
