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TS80C51RB2 Datasheet

  • TS80C51RB2

  • TS87C51RB2. TS80C51RB2 Errata [Updated 4/03. 3 Pages]

  • 3頁

  • ETC

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Active Errata List
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鈥?/div>
鈥?/div>
鈥?/div>
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UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
During UART Reception, Clearing REN May Generate Unexpected IT
JBC/Double IT When External IT Occurs During JBC Instruction
Timer2/Downcounter Mode/Double IT With Slow External Clock
Input Trigger Consumption/All C51 Type I/O Ports
MOVX/Port0/Read Mode
Errata History
TS80C51RB2
Lot Number
Errata List
8051
Microcontrollers
T01, T02 ,T03, T04, T05, T06
T02 ,T03, T04, T05, T06
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38584
> 38584
TS87C51RB2
Lot Number
Errata List
TS87C51RB2
TS80C51RB2
Errata Sheet
鈮?/div>
36425
>
36425
T01, T02 ,T03, T04, T05, T06
T02 ,T03, T04, T05, T06
Errata Descriptions
1. UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
When a false start bit occurs on the UART, some UART internal signals are not reset.
Then when a real start bit occurs, the sampling is shifted.
Workaround
None.
2. During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is clear between a start bit detection and the
end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine just after CLR RI, and run the Interrupt
routine code only if REN is set.
3. JBC/Double IT When External IT Occurs During JBC Instruction
On polling algorithm in ISR on IE1 or IE0, when the external IT appears during JBC
instruction, the flag is not cleared. On the next JBC instruction another IT is pending.
Therefore, the same IT is seen twice.
Workaround
Use JB Instruction instead of JBC instruction to test bit and CLR instruction to clear
it.n twice.
Rev. 4154C鈥?051鈥?4/03
1

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