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TRF2052PW Datasheet

  • TRF2052PW

  • LOW-VOLTAGE 2-GHz SYNTHESIZER

  • 9頁(yè)

  • TI

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TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 鈥?JULY 1998
D
D
D
D
D
3-V Power Supply Operation
2-GHz Operation
Normal and Speed-Up Charge Pumps
Dual PLL: One RF and One IF
Additional, Directly Accessible
Power-Down Modes
PW PACKAGE
(TOP VIEW)
description
The TRF2052 is a dual-channel, low-power,
phase-locked loop (PLL) frequency synthesizer
component designed specifically for digitally en-
hanced cordless telephone (DECT) applications.
The device is suitable for a variety of applications
up through 2 GHz. A speed-up integral charge pump is used for fast channel switching. The simple serial
interface is compatible with the extended performance mode (EPM) of other devices in Texas Instruments鈥?/div>
synthesizer family.
Along with the external loop filters, the TRF2052 provides all functions for voltage-controlled oscillators (VCO)
in a dual-PLL frequency synthesizer system. A main channel is provided for RF frequencies and an auxiliary
channel for IF frequencies. The current-output charge pumps directly drive passive RC filter networks, to
generate VCO control voltages. Fast main-channel frequency switching is achieved with a charge pump
arrangement that increases the current drive and alters the loop-filter frequency response during a portion of
the switching interval.
The speed-up mode is controlled by the serial interface strobe signal, which goes high when a new frequency
is loaded. At this time, the internal speed-up timer is activated and it enables the speed-up mode into the
speed-up timer for the preprogrammed duration. During speed-up mode, the charge pump current to the
external loop filter can be changed in two ways. First, the main charge pump current can be increased. Second,
an additional integral charge pump can be separately and directly connected to the external loop-filter capacitor
to further decrease the loop-filter charge and discharge times.
CLOCK
DATA
STROBE
VSS
RFINP
RFINN
VCCP
REFIN
RA
AUXIN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
NENM
LOCK
NENA
RN
VDDA
PHP
PHI
VSSA
PHA
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device placed in conductive
foam during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
漏
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

TRF2052PW 產(chǎn)品屬性

  • 70

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器

  • -

  • PLL 頻率合成器

  • 是

  • 時(shí)鐘

  • 時(shí)鐘

  • 1

  • 3:3

  • 是/無(wú)

  • 2GHz

  • 是/無(wú)

  • 2.7 V ~ 3.3 V

  • -10°C ~ 55°C

  • 表面貼裝

  • 20-TSSOP（0.173"，4.40mm 寬）

  • 20-TSSOP

  • 管件

  • 296-1969296-1969-5

TRF2052PW相關(guān)型號(hào)PDF文件下載

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