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TQ8223 Datasheet

  • TQ8223

  • ATM/SONET Demultiplexer

  • 212.48KB

  • 22頁

  • ETC

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T
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T
S E M I C O N D U C T O R, I N C .
TQ8223
TELECOM
PRODUCTS
The TQ8223 is a multi-configuration SONET/SDH OC48/STM16 CDR/
DEMUX that regenerates and re-times serial 2.48832 Gb/s data. It
recovers the 2.48832 GHz clock from the data stream and frequency
divides it to generate control signals and clocks used to perform the
demultiplexing function.
The TQ8223 is extremely flexible for telecom, ATM and networking
applications. The serial 2.48832 Gb/s data stream is demultiplexed into a
32-bit wide 77.76 MHz TTL data bus. Internal data inversion is also
available. The device generates byte-wise parity check bits for the
demultiplexed data and provides associated clock outputs for the different
modes. Parity checking is not required for normal device operation.
PRELIMINARY DATA SHEET
OC48/STM16
DEMUX/CDR
with Differential Input
Features
鈥?Single-chip 1:32 Demultiplexer
with integrated clock and data
recovery
鈥?Differential Analog Data Input
鈥?SONET/SDH compliant for
2.48832 Gb/s jitter tolerance &
transfer
鈥?Internal PLL with NRZ phase
detector ensures sampling of
incoming data stream occurs in
center of data eye
鈥?Static phase adjustment on
recovered clock position
鈥?High speed input data bit slipper
for use in framing
鈥?External RC-based loop filter
The TQ8223 provides added flexibility through a selectable internal/external
Voltage Controlled Oscillator(VCO) as well as a selectable internal Phase
Locked Loop (PLL). If an external high frequency clock is utilized a single-
ended or differential AC coupled clock may be used.
The internal PLL contains a NRZ phase detector which enables it to adjust
the phase of the internal clock such that sampling of the incoming data
stream occurs in the middle of the the data eye. An offset control allows
adjustment
鹵125
pS around this nominal position.
Operating from a single +5V supply, the TQ8223 provides fully compliant
functionality and performance.
The TQ8223 is fully compliant with SONET/SDH jitter tolerance and
transfer specifications. A TTL level LOCK signal is supplied to indicate
when the frequency difference between the internal 38.88 MHz clock and
the external 38.88 MHz clock is less than 488 ppm.
鈥?Four output clock rates at
311.04, 155.52, 77.76, and 38.88
MHz.
鈥?Internal byte-wise even/odd
parity bit generator (mode
programable)
鈥?Direct-coupled TTL low-speed
outputs
鈥?23mm 208-pin BGA package
鈥?5V single supply
鈥?鈥?0 to +125
擄
C case operating
temperature.
1

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