TQ8016 Datasheet

IC型號：
TQ8016
PDF描述：
1.3 Gigabit/sec 16x16 Digital ECL Crosspoint Switch
文件大小：
237.01KB
PDF頁數(shù)：
9頁
芯片廠家：
TRIQUINT

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S E M I C O N D U C T O R, I N C .

TQ8016

D0..15

Input

Buffers

16 x 16

Crosspoint

Switch

Matrix

CONFIGURE

(R2)

Sixteen 4-Bit Latches

(R1)

Sixteen 4-Bit Addressable

Output Select Latches

4:16

Decoder

VCC

VEE

OA0..3

TQ8016

GND

Output

Buffers

O0..15

1.3 Gigabit/sec

16x16 Digital ECL

Crosspoint Switch

SWITCHING

PRODUCTS

RESET

LOAD

IA0..3

The TQ8016 is a 16 x 16 differential digital crosspoint switch capable of

handling 1.3 Gbit/s data rate. The high data rate and exceptional signal

fidelity is made possible with TriQuint's fully differential Source-Coupled

FET Logic (SCFL) standard cells. The symmetrical switching characteristic

inherent in differential logic results in low signal skew and crosstalk for

maximum signal fidelity.

The user can independently configure any switch output to any input,

including an input chosen by another output. To configure the switch, the

4-bit output address (OA0..3) is decoded to enable the loading of the 4-bit

input selection data (IA0..3) on the rising edge of the LOAD signal. The

process is repeated until all desired connections are programmed. By

bringing the CONFIGURE signal high, the contents of the Output Select

Latches are transferred in parallel to a second row of 4-bit latches (R2),

causing the switch reconfiguration.

This double row architecture minimizes the time to completely reconfigure

the switch since a new set of addresses can be loaded to the Output Select

Latches (R1) while the switch is active (transmitting). At the time of

reconfiguration, no data drop-out occurs for any output whose input

connection does not change.

For applications which do not require synchronous configuration of the

switch, the LOAD and CONFIGURE inputs may be tied together.

Typical output waveform with

all channels driven

Features

鈥?>1.3 Gigabit/sec data rate

鈥?Non-blocking architecture

鈥?+200 ps delay match (one

input to all outputs)

鈥?/div>

ECL-level data inputs/outputs;

CMOS-level control inputs

鈥?Low crosstalk

鈥?Fully differential data path

鈥?Double row of output select

latches minimizes

reconfiguration time

鈥?Available in 132-pin leaded

chip carrier

For additional information and latest specifications, see our website:

www.triquint.com

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