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TP3064BN Datasheet

  • TP3064BN

  • MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER

  • 301.94KB

  • 21頁

  • TI

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TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D 鈥?MAY 1990 鈥揜EVISED JULY 1996
D
Complete PCM Codec and Filtering
Systems Include:
鈥?Transmit High-Pass and Low-Pass
Filtering
鈥?Receive Low-Pass Filter With (sin x)/x
Correction
鈥?Active RC Noise Filters
鈥?/div>
碌-Law
or A-Law Compatible Coder and
Decoder
鈥?Internal Precision Voltage Reference
鈥?Serial I/O Interface
鈥?Internal Autozero Circuitry
D
D
D
D
D
D
D
D
D
碌-Law
鈥?TP13064B and TP3064B
A-Law 鈥?TP13067B and TP3067B
鹵5
-V Operation
Low Operating Power . . . 70 mW Typ
Power-Down Standby Mode . . . 3 mW Typ
Automatic Power Down
TTL- or CMOS-Compatible Digital Interface
Maximizes Line Interface Card Circuit
Density
Improved Versions of National
Semiconductor TP3064, TP3067, TP3064-X,
and TP3067-X
DW OR N PACKAGE
(TOP VIEW)
description
The TP3064B, TP3067B, TP13064B, and
TP13067B each comprise a single-chip pulse-
code-modulation encoder and decoder (PCM
codec), and PCM line filter. They also provide
band-pass filtering of the analog signals prior to
the encoding, and low-pass filtering after the
decoding of voice signals and call-progress tones.
All the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a time-divi-
sion-multiplexed (TDM) system are included
on-chip. These devices are pin-for-pin compatible
with the National Semiconductor TP3064 and
TP3067. Primary applications include:
VPO+
ANLG GND
VPO 鈥?/div>
VPI
VFRO
V
CC
FSR
DR
BCLKR/CLKSEL
MCLKR/PDN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
BB
VFXI+
VFXI 鈥?/div>
GSX
ANLG LOOP
TSX
FSX
DX
BCLKX
MCLKX
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Line interface for digital transmission and
switching of T1 carrier, PABX (private
automated branch exchange), and central
office telephone systems
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data-storage systems
Digital signal processing
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system, and are intended to be used
at the analog termination of a PCM line or trunk. They require a transmit master clock and a receive master clock
that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are
synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3064B and TP13064B contain patented circuitry to achieve low transmit channel
idle noise and are not recommended for applications in which the composite signals on the transmit side are
below 鈥?55 dBm0.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the CMOS gates.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

TP3064BN 產品屬性

  • 20

  • 集成電路 (IC)

  • 接口 - 編解碼器

  • -

  • PCM 編解碼器/濾波器

  • 串行

  • 8 b

  • 1 / 1

  • 無

  • -

  • -

  • 4.75 V ~ 5.25 V

  • 4.75 V ~ 5.25 V

  • 0°C ~ 70°C

  • 通孔

  • 20-DIP（0.300"，7.62mm）

  • 20-PDIP

  • 管件

  • 296-10792-5

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