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TMX470R1A64PN Datasheet

  • TMX470R1A64PN

  • 16/32-Bit RISC Flash Microcontroller

  • 46頁

  • TI

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TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099 鈥?NOVEMBER 2004
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(1)
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The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not sup-
ported on this device.
ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
Copyright 漏 2004, Texas Instruments Incorporated
ADVANCE INFORMATION
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High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI鈩?
鈥?24-MHz System Clock (48-MHz Pipeline
Mode)
鈥?Independent 16/32-Bit Instruction Set
鈥?Open Architecture With Third-Party Support
鈥?Built-In Debug Module
鈥?Big-Endian Format Utilized
Integrated Memory
鈥?64K-Byte Program Flash
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One Bank With Five Contiguous Sectors
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Internal State Machine for Programming
and Erase
鈥?4K-Byte Static RAM (SRAM)
Operating Features
鈥?Core Supply Voltage (VCC): 1.71 V鈥?.05 V
鈥?I/O Supply Voltage (VCCIO): 3.0 V鈥?.6 V
鈥?Low-Power Modes: STANDBY and HALT
鈥?Industrial Temperature Ranges
470+ System Module
鈥?32-Bit Address Space Decoding
鈥?Bus Supervision for Memory and
Peripherals
鈥?Analog Watchdog (AWD) Timer
鈥?Real-Time Interrupt (RTI)
鈥?System Integrity and Failure Detection
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
鈥?Multiply-by-4 or -8 Internal ZPLL Option
鈥?ZPLL Bypass Mode
Six Communication Interfaces:
鈥?Two Serial Peripheral Interfaces (SPIs)
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255 Programmable Baud Rates
鈥?Two Serial Communication Interfaces (SCIs)
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2
24
Selectable Baud Rates
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Asynchronous/Isosynchronous Modes
鈥?Standard CAN Controller (SCC)
鈥?16-Mailbox Capacity
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Fully Compliant With CAN Protocol, Version
2.0B
鈥?Class II Serial Interface (C2SIa)
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Two Selectable Data Rates
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Normal Mode 10.4 Kbps and 4X Mode 41.6
Kbps
High-End Timer (HET)
鈥?13 Programmable I/O Channels:
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12 High-Resolution Pins
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1 Standard-Resolution Pin
鈥?High-Resolution Share Feature (XOR)
鈥?HET RAM (64-Instruction Capacity)
10-Bit Multi-Buffered ADC (MibADC)
8-Channel
鈥?64-Word FIFO Buffer
鈥?Single- or Continuous-Conversion Modes
鈥?1.55
碌s
Minimum Sample and Conversion
Time
鈥?Calibration Mode and Self-Test Features
Six External Interrupts
Flexible Interrupt Handling
5 Dedicated General-Purpose I/O (GIO) Pins, 1
Input-Only GIO Pin, and 34 Additional
Peripheral I/Os
External Clock Prescale (ECP) Module
鈥?Programmable Low-Frequency External
Clock (CLK)
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1
(1)
(JTAG) Test-Access Port
80-Pin Plastic Low-Profile Quad Flatpack (PN
Suffix)

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