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TMX320DM6443AZWT Datasheet

  • TMX320DM6443AZWT

  • Digital Media System-on-Chip

  • 221頁

  • TI

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TMS320DM6443
Digital Media System-on-Chip
SPRS282E 鈥?DECEMBER 2005 鈥?REVISED MARCH 2007
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
鈥?/div>
High-Performance Digital Media SoC
鈥?594-MHz C64x+鈩?Clock Rate
鈥?297-MHz ARM926EJ-S鈩?Clock Rate
鈥?Eight 32-Bit C64x+ Instructions/Cycle
鈥?4752 C64x+ MIPS
鈥?Fully Software-Compatible With C64x /
ARM9鈩?/div>
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+鈩?DSP Core
鈥?Eight Highly Independent Functional Units
鈥?/div>
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
鈥?/div>
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
鈥?Load-Store Architecture With Non-Aligned
Support
鈥?64 32-Bit General-Purpose Registers
鈥?Instruction Packing Reduces Code Size
鈥?All Instructions Conditional
鈥?Additional C64x+鈩?Enhancements
鈥?/div>
Protected Mode Operation
鈥?/div>
Exceptions Support for Error Detection
and Program Redirection
鈥?/div>
Hardware Support for Modulo Loop
Operation
C64x+ Instruction Set Features
鈥?Byte-Addressable (8-/16-/32-/64-Bit Data)
鈥?8-Bit Overflow Protection
鈥?Bit-Field Extract, Set, Clear
鈥?Normalization, Saturation, Bit-Counting
鈥?Compact 16-Bit Instructions
鈥?Additional Instructions to Support Complex
Multiplies
C64x+ L1/L2 Memory Architecture
鈥?32K-Byte L1P Program RAM/Cache (Direct
Mapped)
鈥?80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
鈥?64K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
鈥?/div>
ARM926EJ-S Core
鈥?Support for 32-Bit and 16-Bit (Thumb廬
Mode) Instruction Sets
鈥?DSP Instruction Extensions and Single
Cycle MAC
鈥?ARM廬 Jazelle廬 Technology
鈥?EmbeddedICE-RT鈩?Logic for Real-Time
Debug
ARM9 Memory Architecture
鈥?16K-Byte Instruction Cache
鈥?8K-Byte Data Cache
鈥?16K-Byte RAM
鈥?8K-Byte ROM
Emulation Trace Buffer鈩?(ETB11鈩? With 4-KB
Memory for ARM9 Debug
Endianness: Little Endian for ARM and DSP
Video Processing Subsystem
鈥?Resize Engine Provides:
鈥?/div>
Resize Images From 1/4x to 4x
鈥?/div>
Separate Horizontal and Vertical Control
鈥?Back End Provides:
鈥?/div>
Hardware On-Screen Display (OSD)
鈥?/div>
4 - 54 MHz DACs for a Combination of
鈥?/div>
Composite NTSC/PAL Video
鈥?/div>
Luma/Chroma Separate Video
(S-video)
鈥?/div>
Component (YPbPr or RGB) Video
(Progressive)
鈥?/div>
Digital Output
鈥?/div>
8-/16-Bit YUV or up to 24-Bit RGB
鈥?/div>
HD Resolution
鈥?/div>
Up to 2 Video Windows
External Memory Interfaces (EMIFs)
鈥?32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
鈥?Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
鈥?/div>
Flash Memory Interfaces
鈥?/div>
NOR (8-/16-Bit-Wide Data)
鈥?/div>
NAND (8-/16-Bit-Wide Data)
Flash Card Interfaces
鈥?Multimedia Card (MMC)/Secure Digital (SD)
with Secure Data I/O (SDIO)
鈥?Compact Flash Controller With True IDE
Mode
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2005鈥?007, Texas Instruments Incorporated

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