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TMS32C6414EZLZ6E3 Datasheet

  • TMS32C6414EZLZ6E3

  • FIXED-POINT DIGITAL SIGNAL PROCESSORS

  • 141頁(yè)

  • TI

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TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
鈭?/div>
FEBRUARY 2001
鈭?/div>
REVISED MAY 2005
D
Highest-Performance Fixed-Point Digital
D
D
D
D
D
Signal Processors (DSPs)
鈭?/div>
2-, 1.67-, 1.39-ns Instruction Cycle Time
鈭?/div>
500-, 600-, 720-MHz Clock Rate
鈭?/div>
Eight 32-Bit Instructions/Cycle
鈭?/div>
Twenty-Eight Operations/Cycle
鈭?/div>
4000, 4800, 5760 MIPS
鈭?/div>
Fully Software-Compatible With C62x鈩?/div>
鈭?/div>
C6414/15/16 Devices Pin-Compatible
VelociTI.2鈩?Extensions to VelociTI鈩?/div>
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x鈩?DSP Core
鈭?/div>
Eight Highly Independent Functional
Units With VelociTI.2鈩?Extensions:
鈭?/div>
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
鈭?/div>
Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
鈭?/div>
Non-Aligned Load-Store Architecture
鈭?/div>
64 32-Bit General-Purpose Registers
鈭?/div>
Instruction Packing Reduces Code Size
鈭?/div>
All Instructions Conditional
Instruction Set Features
鈭?/div>
Byte-Addressable (8-/16-/32-/64-Bit Data)
鈭?/div>
8-Bit Overflow Protection
鈭?/div>
Bit-Field Extract, Set, Clear
鈭?/div>
Normalization, Saturation, Bit-Counting
鈭?/div>
VelociTI.2鈩?Increased Orthogonality
Viterbi Decoder Coprocessor (VCP) [C6416]
鈭?/div>
Supports Over 600 7.95-Kbps AMR
鈭?/div>
Programmable Code Parameters
Turbo Decoder Coprocessor (TCP) [C6416]
鈭?/div>
Supports up to 7 2-Mbps or
43 384-Kbps 3GPP (6 Iterations)
鈭?/div>
Programmable Turbo Code and
Decoding Parameters
L1/L2 Memory Architecture
鈭?/div>
128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
鈭?/div>
128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
鈭?/div>
8M-Bit (1024K-Byte) L2 Unified Mapped
RAM/Cache (Flexible Allocation)
D
Two External Memory Interfaces (EMIFs)
D
D
D
D
D
D
D
D
D
D
D
D
D
鈭?/div>
One 64-Bit (EMIFA), One 16-Bit (EMIFB)
鈭?/div>
Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
鈭?/div>
1280M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Host-Port Interface (HPI)
鈭?/div>
User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave
Interface Conforms to PCI Specification 2.2
[C6415/C6416 ]
鈭?/div>
Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
鈭?/div>
Four-Wire Serial EEPROM Interface
鈭?/div>
PCI Interrupt Request Under DSP
Program Control
鈭?/div>
DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports
鈭?/div>
Direct I/F to T1/E1, MVIP, SCSA Framers
鈭?/div>
Up to 256 Channels Each
鈭?/div>
ST-Bus-Switching-, AC97-Compatible
鈭?/div>
Serial Peripheral Interface (SPI)
Compatible (Motorola鈩?
Three 32-Bit General-Purpose Timers
Universal Test and Operations PHY
Interface for ATM (UTOPIA) [C6415/C6416]
鈭?/div>
UTOPIA Level 2 Slave ATM Controller
鈭?/div>
8-Bit Transmit and Receive Operations
up to 50 MHz per Direction
鈭?/div>
User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package
(GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball
Pitch
0.13-碌m/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
鈥?/div>
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
2005 Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈭?443
1

TMS32C6414EZLZ6E3 產(chǎn)品屬性

  • 1

  • 集成電路 (IC)

  • 嵌入式 - DSP（數(shù)字式信號(hào)處理器）

  • TMS320C6414T/15T/16T

  • 定點(diǎn)

  • 主機(jī)接口，McBSP

  • 600MHz

  • 外部

  • 1.03MB

  • 3.30V

  • 1.40V

  • 0°C ~ 90°C

  • 表面貼裝

  • 532-BFBGA，F(xiàn)CBGA

  • 532-FCBGA（23x23）

  • 托盤

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