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TMS320LC549PGE Datasheet

  • TMS320LC549PGE

  • FIXED-POINT DIGITAL SIGNAL PROCESSOR

  • 61頁

  • TI

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TMS320LC549
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS077B 鈥?SEPTEMBER 1998 鈥?REVISED FEBRUARY 2000
D
Advanced Multibus Architecture With Three
D
D
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17-
脳
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Address Bus With a Bus Holder Feature
Extended Addressing Mode for 8M
脳
16-Bit
Maximum Addressable External Program
Space
192K
脳
16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O)
On-Chip ROM with Some Configurable to
Program/Data Memory
Dual-Access On-Chip RAM
Single-Access On-Chip RAM
Single-Instruction Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
D
Instructions With a 32-Bit Long Word
D
D
D
D
D
Operand
Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
鈥?Software-Programmable Wait-State
Generator and Programmable Bank
Switching
鈥?On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
鈥?Time-Division Multiplexed (TDM) Serial
Port
鈥?Buffered Serial Port (BSP)
鈥?8-Bit Parallel Host-Port Interface (HPI)
鈥?One 16-Bit Timer
鈥?External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
鈥?/div>
(JTAG) Boundary Scan
Logic
15-ns Single-Cycle Fixed-Point Instruction
Execution Time (66 MIPS) for 3.3-V Power
Supply
12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply
D
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
鈥?IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
2000, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1

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