TMS320C6455 Datasheet

IC型號(hào)：
TMS320C6455
PDF描述：
Fixed-Point Digital Signal Processor
文件大?。?/label>
969.09KB
PDF頁(yè)數(shù)：
116頁(yè)
芯片廠家：
TI

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www.ti.com

TMS320C6455 Fixed-Point Digital Signal Processor

SPRS276 鈥?MAY 2005

1.1

鈥?/div>

TMS320C6455 Fixed-Point Digital Signal Processor

Features

鈥?/div>

EDMA Controller (64 Independent Channels)

Four 1x Serial RapidIO廬 Links (or One 4x),

v1.2 Compliant

鈥?1.25-, 2.5-, 3.125-Gbps Link Rates

鈥?Message Passing, DirectIO Support, Error

Management Extensions, and Congestion

Control

鈥?IEEE 1149.6 Compliant I/Os

32-/16-Bit Host-Port Interface (HPI)

32-Bit/66-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface

Conforms to PCI Specification 2.3

One Inter-Integrated Circuit (I

C) Bus

Two Multichannel Buffered Serial Ports

(McBSPs)

10/100/1000 Mb/s Ethernet MAC (EMAC)

鈥?IEEE 802.3 Compliant

鈥?Supports Multiple Media Independent

Interfaces

(MII, GMII, RMII, and RGMII)

鈥?8 Independent Transmit (TX) and

8 Independent Received (RX) Channels

Two 64-Bit General-Purpose Timers,

Configurable as Four 32-Bit Timers

Universal Test and Operations PHY Interface

for ATM (UTOPIA)

鈥?UTOPIA Level 2 Slave ATM Controller

鈥?8-Bit Transmit and Receive Operations up

to 50 MHz per Direction

鈥?User-Defined Cell Format up to 64 Bytes

16 General-Purpose I/O (GPIO) Pins

PLL1 and PLL1 Controller

PLL2 Dedicated for DDR2 EMIF and EMAC

IEEE-1149.1 (JTAG)

Boundary-Scan-Compatible

697-Pin Ball Grid Array (BGA) Package

(ZTZ Suffix), 0.8-mm Ball Pitch

0.09-碌m/7-Level Cu Metal Process (CMOS)

3.3-, 1.8-, 1.5-, 1.2-V I/Os, 1.2-V Internal

鈥?/div>

High-Performance Fixed-Point DSP (C6455)

鈥?1.39-, 1.17-, 1-ns Instruction Cycle Time

鈥?720-, 850-MHz and 1-GHz Clock Rate

鈥?Eight 32-Bit Instructions/Cycle

鈥?5760, 6800, 8000 MIPS

鈥?5760, 6800, 8000 MMACS (16 Bits)

鈥?Commercial Temperature [0擄C to 90擄C]

TMS320C64x+鈩?DSP Core

鈥?Dedicated SPLOOP Instruction

鈥?Compact Instructions (32-/16-Bit)

鈥?Instruction Set Enhancements

鈥?Exception Handling

TMS320C64x+ Megamodule

L1/L2 Memory Architecture:

鈥?256K-Bit (32K-Byte) L1P Program Cache

[Direct Mapped]

鈥?256K-Bit (32K-Byte) L1D Data Cache

[2-Way Set-Associative]

鈥?16M-Bit (2048K-Byte) L2 Unified Mapped

RAM/Cache [Flexible Allocation]

Enhanced Viterbi Decoder Coprocessor (VCP2)

鈥?Supports Over 694 7.95-Kbps AMR

鈥?Programmable Code Parameters

Enhanced Turbo Decoder Coprocessor (TCP2)

鈥?Supports up to Eight 2-Mbps 3GPP

(6 Iterations)

鈥?Programmable Turbo Code and Decoding

Parameters

Endianess: Little Endian, Big Endian

64-Bit/133-MHz EMIFA

鈥?Glueless Interface to Asynchronous

Memories (SRAM, Flash, and EPROM)

鈥?Glueless Interface to Synchronous

Memories (SBSRAM and ZBT SRAM)

鈥?Supports Interface to Standard Sync

Devices

鈥?Sync or Async Interface to Custom Logic

(FPGA, CPLD, ASICs, etc.)

鈥?32M-Byte Total Addressable External

Memory Space (8MB per CE space)

32-Bit DDR2 EMIF (DDR2-500 SDRAM)

鈥?/div>

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

All trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the forma-

tive or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the

right to change or discontinue these products without notice.

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