TMS320C6424_1 Datasheet

IC型號：
TMS320C6424_1
PDF描述：
Fixed-Point Digital Signal Processor
文件大?。?/label>
1990.75KB
PDF頁數(shù)：
245頁
芯片廠家：
TI

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www.ti.com

TMS320C6424

Fixed-Point Digital Signal Processor

SPRS347B 鈥?MARCH 2007 鈥?REVISED NOVEMBER 2007

1 TMS320C6424 Fixed-Point Digital Signal Processor

1.1 Features

鈥?/div>

High-Performance Digital Signal Processor

(C6424)

鈥?2.5-, 2-, 1.67-ns Instruction Cycle Time

鈥?400-, 500-, 600-MHz C64x+鈩?Clock Rate

鈥?Eight 32-Bit C64x+ Instructions/Cycle

鈥?3200, 4000, 4800 MIPS

鈥?Fully Software-Compatible With C64x

鈥?Commercial and Automotive (Q or S suffix)

Grades

VelociTI.2鈩?Extensions to VelociTI鈩?/div>

Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x+鈩?DSP Core

鈥?Eight Highly Independent Functional Units

With VelociTI.2 Extensions:

鈥?/div>

Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

Arithmetic per Clock Cycle

鈥?/div>

Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

Results) per Clock Cycle

鈥?Load-Store Architecture With Non-Aligned

Support

鈥?64 32-Bit General-Purpose Registers

鈥?Instruction Packing Reduces Code Size

鈥?All Instructions Conditional

鈥?Additional C64x+鈩?Enhancements

鈥?/div>

Protected Mode Operation

鈥?/div>

Exceptions Support for Error Detection

and Program Redirection

鈥?/div>

Hardware Support for Modulo Loop

Auto-Focus Module Operation

C64x+ Instruction Set Features

鈥?Byte-Addressable (8-/16-/32-/64-Bit Data)

鈥?8-Bit Overflow Protection

鈥?Bit-Field Extract, Set, Clear

鈥?Normalization, Saturation, Bit-Counting

鈥?VelociTI.2 Increased Orthogonality

鈥?C64x+ Extensions

鈥?/div>

Compact 16-bit Instructions

鈥?/div>

Additional Instructions to Support

Complex Multiplies

鈥?/div>

C64x+ L1/L2 Memory Architecture

鈥?256K-Bit (32K-Byte) L1P Program

RAM/Cache [Flexible Allocation]

鈥?640K-Bit (80K-Byte) L1D Data RAM/Cache

[Flexible Allocation]

鈥?1M-Bit (128K-Byte) L2 Unified Mapped

RAM/Cache [Flexible Allocation]

Endianess: Supports Both Little Endian and

Big Endian

External Memory Interfaces (EMIFs)

鈥?32-Bit DDR2 SDRAM Memory Controller

With 256M-Byte Address Space (1.8-V I/O)

鈥?/div>

Supports up to 333-MHz (data rate) bus

and interfaces to DDR2-400 SDRAM

鈥?Asynchronous 16-Bit Wide EMIF (EMIFA)

With up to 128M-Byte Address Reach

鈥?/div>

Flash Memory Interfaces

鈥?NOR (8-/16-Bit-Wide Data)

鈥?NAND (8-/16-Bit-Wide Data)

Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

Two 64-Bit General-Purpose Timers (Each

Configurable as Two 32-Bit Timers)

One 64-Bit Watch Dog Timer

Two UARTs (One with RTS and CTS Flow

Control)

Master/Slave Inter-Integrated Circuit (I

Bus鈩?

Two Multichannel Buffered Serial Ports

(McBSPs)

鈥?I2S and TDM

鈥?AC97 Audio Codec Interface

鈥?SPI

鈥?Standard Voice Codec Interface (AIC12)

鈥?Telecom Interfaces 鈥?ST-Bus, H-100

鈥?128 Channel Mode

Multichannel Audio Serial Port (McASP0)

鈥?Four Serializers and SPDIF (DIT) Mode

16-Bit Host-Port Interface (HPI)

32-Bit 33-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface

鈥?/div>

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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