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TMS320C6204-200 Datasheet

  • TMS320C6204-200

  • Fixed-Point Digital Signal Processor

  • 81頁

  • ETC

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TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS152A 鈥?OCTOBER 2000 鈥?REVISED JUNE 2001
D
High-Performance Fixed-Point Digital
Signal Processor (DSP) 鈥?TMS320C6204
鈥?5-ns Instruction Cycle Time
鈥?200-MHz Clock Rate
鈥?Eight 32-Bit Instructions/Cycle
鈥?1600 MIPS
C6204 GLW Ball Grid Array (BGA) Package
is Pin-Compatible With the C6202/02B/03
GLS BGA Package
鈥?/div>
VelociTI錚?Advanced Very-Long-Instruction-
Word (VLIW) TMS320C62x錚?DSP Core
鈥?Eight Highly Independent Functional
Units:
鈥?Six ALUs (32-/40-Bit)
鈥?Two 16-Bit Multipliers (32-Bit Result)
鈥?Load-Store Architecture With 32 32-Bit
General-Purpose Registers
鈥?Instruction Packing Reduces Code Size
鈥?All Instructions Conditional
Instruction Set Features
鈥?Byte-Addressable (8-, 16-, 32-Bit Data)
鈥?8-Bit Overflow Protection
鈥?Saturation
鈥?Bit-Field Extract, Set, Clear
鈥?Bit-Counting
鈥?Normalization
1M-Bit On-Chip SRAM
鈥?512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
鈥?512K-Bit Dual-Access Internal Data
(64K Bytes)
鈥?Organized as Two 32K-Byte Blocks for
Improved Concurrency
32-Bit External Memory Interface (EMIF)
鈥?Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
鈥?Glueless Interface to Asynchronous
Memories: SRAM and EPROM
鈥?52M-Byte Addressable External Memory
Space
D
Four-Channel Bootloading
D
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
32-Bit Expansion Bus (XB)
鈥?Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
鈥?Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
鈥?Master/Slave Functionality
鈥?Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
Two Multichannel Buffered Serial Ports
(McBSPs)
鈥?Direct Interface to T1/E1, MVIP, SCSA
Framers
鈥?ST-Bus-Switching Compatible
鈥?Up to 256 Channels Each
鈥?AC97-Compatible
鈥?Serial-Peripheral Interface (SPI)
Compatible (Motorola錚?
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
288-Pin MicroStar BGA錚?Package (GHK)
340-Pin BGA Package (GLW)
0.15-碌m/5-Level Metal Process
鈥?CMOS Technology
3.3-V I/Os, 1.5-V Internal
D
D
D
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D
D
D
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
鈥?/div>
For more details, see the GLW BGA package bottom view.
鈥?/div>
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright
錚?/div>
2001, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1
ADVANCE INFORMATION

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