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TMS320C6203BGNZ173 Datasheet

  • TMS320C6203BGNZ173

  • FIXED-POINT DIGITAL SIGNAL PROCESSOR

  • 106頁

  • TI

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TMS320C6203B
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086M
鈭?/div>
JANUARY 1999
鈭?/div>
REVISED MARCH 2004
D
High-Performance Fixed-Point Digital
D
D
D
D
D
D
Signal Processor (DSP)
鈭?/div>
TMS320C62x錚?/div>
鈭?/div>
4-, 3.33-ns Instruction Cycle Time
鈭?/div>
250-, 300-MHz Clock Rate
鈭?/div>
Eight 32-Bit Instructions/Cycle
鈭?/div>
2000, 2400 MIPS
C6203B and C6202 GLS Ball Grid Array
(BGA) Packages are Pin-Compatible With
the C6204 GLW BGA Package
鈥?/div>
C6203B and C6202B GNZ and GNY
Packages are Pin-Compatible
VelociTI錚?Advanced Very-Long-Instruction-
Word (VLIW) C62x錚?DSP Core
鈭?/div>
Eight Highly Independent Functional
Units:
鈭?/div>
Six ALUs (32-/40-Bit)
鈭?/div>
Two 16-Bit Multipliers (32-Bit Result)
鈭?/div>
Load-Store Architecture With 32 32-Bit
General-Purpose Registers
鈭?/div>
Instruction Packing Reduces Code Size
鈭?/div>
All Instructions Conditional
Instruction Set Features
鈭?/div>
Byte-Addressable (8-, 16-, 32-Bit Data)
鈭?/div>
8-Bit Overflow Protection
鈭?/div>
Saturation
鈭?/div>
Bit-Field Extract, Set, Clear
鈭?/div>
Bit-Counting
鈭?/div>
Normalization
7M-Bit On-Chip SRAM
鈭?/div>
3M-Bit Internal Program/Cache
(96K 32-Bit Instructions)
鈭?/div>
4M-Bit Dual-Access Internal Data
(512K Bytes)
鈭?/div>
Organized as Two 256K-Byte Blocks
for Improved Concurrency
32-Bit External Memory Interface (EMIF)
鈭?/div>
Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
鈭?/div>
Glueless Interface to Asynchronous
Memories: SRAM and EPROM
鈭?/div>
52M-Byte Addressable External Memory
Space
D
Four-Channel Bootloading
D
D
D
D
D
D
D
D
D
D
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
Flexible Phase-Locked-Loop (PLL) Clock
Generator
32-Bit Expansion Bus (XBus)
鈭?/div>
Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
鈭?/div>
Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
鈭?/div>
Master/Slave Functionality
鈭?/div>
Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
Three Multichannel Buffered Serial Ports
(McBSPs)
鈭?/div>
Direct Interface to T1/E1, MVIP, SCSA
Framers
鈭?/div>
ST-Bus-Switching Compatible
鈭?/div>
Up to 256 Channels Each
鈭?/div>
AC97-Compatible
鈭?/div>
Serial-Peripheral Interface (SPI)
Compatible (Motorola錚?
Two 32-Bit General-Purpose Timers
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
352-Pin BGA Package (GNZ)
384-Pin BGA Package (GLS)
384-Pin BGA Package (GNY)
0.15-碌m/5-Level Metal Process
鈭?/div>
CMOS Technology
3.3-V I/Os, 1.5-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
鈥?/div>
For more details, see the GLS BGA package bottom view.
鈥?/div>
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2004, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈭?443
1

TMS320C6203BGNZ173 產品屬性

  • 40

  • 集成電路 (IC)

  • 嵌入式 - DSP（數(shù)字式信號處理器）

  • TMS320C62x

  • 定點

  • McBSP

  • -

  • 外部

  • 896kB

  • 3.30V

  • 1.50V

  • 0°C ~ 90°C

  • 表面貼裝

  • 352-BBGA，F(xiàn)CBGA

  • 352-FCBGA（27x27）

  • 托盤

  • 296-15124-5

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