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TMS320C30-40 Datasheet

  • TMS320C30-40

  • Digital Signal Processor

  • 53頁

  • ETC

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TMS320C30
DIGITAL SIGNAL PROCESSOR
SPRS032A 鈥?APRIL 1996 鈥?REVISED JUNE 1997
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High-Performance Floating-Point Digital
Signal Processor (DSP)
鈥?TMS320C30-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
鈥?TMS320C30-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
鈥?TMS320C30-33 (5 V)
60-ns Instruction Cycle Time
183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS
鈥?TMS320C30-27 (5 V)
74-ns Instruction Cycle Time
148.5 MOPS, 27 MFLOPS, 13.5 MIPS
32-Bit High-Performance CPU
16- / 32-Bit Integer and 32- / 40-Bit
Floating-Point Operations
32-Bit Instruction Word, 24-Bit Addresses
Two 1K
脳
32-Bit Single-Cycle Dual-Access
On-Chip RAM Blocks
One 4K
脳
32-Bit Single-Cycle Dual-Access
On-Chip ROM Block
On-Chip Memory-Mapped Peripherals:
鈥?Two Serial Ports
鈥?Two 32-Bit Timers
鈥?One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
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Two 32-Bit External Ports
24- and 13-Bit Addresses
0.7-碌m Enhanced Performance Implanted
CMOS (EPIC鈩? Technology
208-Pin Plastic Quad Flat Package
( PPM Suffix )
181-Pin Grid Array Ceramic Package
(GEL Suffix)
Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two- and Three-Operand Instructions
Parallel Arithmetic and Logic Unit (ALU)
and Multiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
Two Sets of Memory Strobes (STRB and
MSTRB) and One I / O Strobe (IOSTRB)
Separate Bus-Control Registers for Each
Strobe-Control Wait-State Generation
description
The TMS320C30 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TI鈩?.
The TMS320C30 is a 32-bit floating-point processor manufactured in 0.7-碌m triple-level-metal CMOS
technology.
The TMS320C30鈥檚 internal busing and special DSP instruction set have the speed and flexibility to execute up
to 50 MFLOPS (million floating-point operations per second). The TMS320C30 optimizes speed by
implementing functions in hardware that other processors implement through software or microcode. This
hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I / O, and a short machine-cycle time.
High performance and ease of use are results of these features.
General-purpose applications are enhanced greatly by the large address space, multiprocessor interface,
internally and externally generated wait states, two external interface ports, two timers, serial ports, and multiple
interrupt structure. The TMS320C30 supports a wide variety of system applications from host processor to
dedicated coprocessor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1997, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
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