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TI380PCIA Datasheet

  • TI380PCIA

  • PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

  • 40頁

  • TI

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TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS鈩?/div>
SPWS035 鈥?JUNE 1997
D
D
D
D
D
D
D
D
Glueless Interface Between the Peripheral
Component Interconnect (PCI) Bus and the
TI380C2x
鈥?/div>
and TI380C3x
鈥?/div>
Generation of
Processors
Compliant With PCI Specification,
Revision 2.0
鈥÷?/div>
Allows Use of Existing TI2000 Drivers
Includes TI2000 Interface Configuration
Register
Supports Bus Master Operations for High
Performance
Provides 32-Bit Address-Data Path
Implements Address / Data Parity Checking
Includes Internal Error Checking for Illegal
Bus Operations
D
D
D
D
D
D
D
Supports Direct Memory Access (DMA)
Bursts With 64-Byte FIFO
Supports EPROM Interface for Remote
Program Load (RPL) Operation
Supports Inter-Integrated Circuit (I
2
C)
Interface for Optional Serial EEPROM for
Configuration Information
Allows Burned-In Address (BIA) to be
Implemented in Configuration EEPROM
Includes NAND Tree Structure to Allow for
In-Circuit Connectivity Testing
144-Pin JEDEC Plastic Quad Flat Package
(PCM Suffix)
Operating Temperature Range
0
_
C to 70
_
C
The TI380PCIA provides a glueless interface between a TI380C2x
鈥?/div>
commprocessor and the PCI bus (see
Figure 1). The TI380PCIA transfers information / data between the PCI bus and the TI380C2x
鈥?/div>
system interface
(SIF ) using any of these three methods:
D
Direct memory access (DMA)
D
Direct input / output (DIO)
D
Pseudo-direct memory access (PDMA)
DMA (or PDMA) transfers all data between host memory (by way of the PCI local bus) and TI380C2x
鈥?/div>
local
memory. DIO accesses are typically used to load software into TI380C2x
鈥?/div>
local memory and for initializing the
TI380C2x
鈥?/div>
.
The TI380PCIA conforms to the PCI standards found in 鈥淧CI Local Bus Specification,鈥?Revision 2.0.
鈥÷?/div>
The TI380PCIA is available in a 144-pin JEDEC plastic quad flat package (PCM suffix) and is rated from 0
_
C
to 70
_
C. It is a drop-in replacement for the TI380PCI.
EEPROM
PacketBlaster
鈩?/div>
Frame-Processing
Accelerator (FPA)
SIF
PCI Bus
TI380PCIA
TI380C2x鈥?/div>
DRAM
RPL
ROM
Physical
Layer
To Network
Figure 1. TI380PCIA Applications Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
鈥?TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.
鈥?The 鈥淧CI Local Bus Specification鈥? Revision 2.0, and the TI380C2x or TI380C3x series of data sheets (e.g., literature number SPWS012) should
be used as references to this document.
摟 Exceptions to electrical timing parameters specified in PCI Specification Revision 2.0 are described in Note 8 and Note 10 of the timing
requirements section of this document.
PacketBlaster and Commprocessor are trademarks of Texas Instruments Incorporated.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright
漏
1997, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1
ADVANCE INFORMATION
description

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