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TFP403 Datasheet

  • TFP403

  • TI PANEBUS DIGITAL RECEIVER

  • 18頁

  • TI

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TFP403
TI
PanelBus錚?/div>
DIGITAL RECEIVER
SLDS125A 鈥?DECEMBER 2000 鈥?REVISED OCTOBER 2002
D
Supports UXGA Resolution (Output Pixel
D
D
D
D
D
Rates up to 165 MHz)
Digital Visual Interface (DVI 1.0)
Specification Compliant
1
Pin-for-Pin Compatible With TFP501 for
Simple Upgrade Path to HDCP
2
True-Color, 24 Bit/Pixel, 16.7M Colors at
1 or 2-Pixels per Clock
Laser Trimmed (50
鈩?
Input Stage for
Optimum Fixed Impedance Matching
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance)
D
4x Over-Sampling for Reduced Bit-Error
D
D
D
D
D
Rates and Better Performance Over Longer
Cables
Reduced Power Consumption鈥?.8-V Core
Operation With 3.3 V I/Os and Supplies
3
Reduced Ground Bounce Using Time
Staggered Pixel Outputs
Lowest Noise and Best Power Dissipation
Using PowerPAD錚?Packaging
Advanced Technology Using TI 0.18-碌m
EPIC-5錚?CMOS Process
Supports Hot Plug Detection
description
The Texas Instruments TFP403 is a
PanelBus錚?/div>
flat panel display products, part of a comprehensive family of
end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the
TFP403 finds applications in any design requiring high-speed digital interface.
The TFP403 supports display resolutions up to UXGA in 24-bit true color pixel format. The TFP403 offers design
flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time
staggered pixel outputs for reduced ground bounce.
PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultralow
ground inductance.
The TFP403 combines
PanelBus錚?/div>
circuit innovation with TIs advanced 0.18-碌m EPIC-5錚?CMOS process
technology, along with PowerPAD錚?package technology to achieve a reliable, low-powered, low-noise,
high-speed digital interface solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1.
2.
3.
The Digital Visual Interface Specification (DVI) is an industry standard developed by the Digital Display Working Group (DDWG) for
high-speed digital connection to digital displays. The TFP403 is compliant with the DVI Specification Rev. 1.0.
High-bandwidth digital content protection (HDCP) is the system used for protecting DVI outputs from being copied. The TFP501 is
TI鈥檚 DVI receiver with HDCP functionality.
The TFP403 has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies.
PanelBus,
PowerPAD, and EPIC-5 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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