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TDA7500 Datasheet

  • TDA7500

  • DIGITAL AM/FM SIGNAL PROCESSOR

  • 14頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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TDA7500
DIGITAL AM/FM SIGNAL PROCESSOR
PRODUCT PREVIEW
FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES
AM/FM PROCESSING
AUDIO-PROCESSING AND SOUND-PROC-
ESSING
HARDWARE RDS FILTER, DEMODULATOR
& DECODER
INTEGRATED CODEC
IIC AND SPI CONTROL INTERFACES
SPI DEDICATED TO DISPLAY MICRO
6 CHANNEL SERIAL AUDIO INTERFACE SAI
SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER
EXTERNAL MEMORY INTERFACE
DOUBLE DEBUG INTERFACE
ON-CHIP PLL
5V-TOLERANT 3V I/O INTERFACE
MULTIFUNCTION GENERAL PURPOSE I/O PORTS
BLOCK DIAGRAM
Mute
TQFP100 Power with Slug Down
DESCRIPTION
The TDA7500 is an integrated circuit implement-
ing a fully digital, integrated and advanced solu-
tion to perform the signal processing in front of
the power amplifier and behind the AM/FM tuner
or any other audio sources. The chip integrates
two 43 MIPs DSP cores: one for stereo decoding,
noise blanking, weak signal processing and multi-
analog audio in
AM-IF
CC
CD
tel,navi
AM/FM lev.
AM/FM mpx
RDS mpx
1
2
3
4
2
3
1
supply Cref
2
2
AM
Noise
Detector
VS
3
SigGnd RefOut
Input Multiplexer,
Analog Level Adjust
IIC
2 channel analog bypass
CODEC-ref
Output
Analog Volume Control,
select.
Line Driver
6
signal/line out
4
危鈭?/div>
Modulator
危鈭?/div>
Modulator
危鈭?/div>
Modulator
危鈭?/div>
Modulator
Main micro
VDD GND
3
2
Decimation
Filter
Decimation
Filter
DAC-ref
6
Voltage
Ref.
Codec
Ctl Reg.
Test I/F
uP control (4 I/O's)
4
IIC / SPI
SPI
XTAL Osc.,
PLL
Ext. Memory
Interface
Serial Audio
Interface
SPDIF
Interface
Mux
Grp & blk
RDS
sync., error Demod.
Filter
correction
Exchange
Interface
Oversampling
Filter
Oversampling
Filter
Oversampling
Filter
Noise
Shaper
Noise
Shaper
Noise
Shaper
X bus 0
SC Filter
SC Filter
SC Filter
SC Filter
SC Filter
SC Filter
X Register
Ram 512
Y Register
Ram 512
Program
Ram 5632
Rom 256
Display uP (4 I/O's)
4
Spectrum Analyser
CLK in
Audio Bus Synch.
8.55MHz
Data, ctl
8+3
128k (4M) x 8
17
Address
(1 I/O)
Audio Bus 6 ch.
3
dig. aud. out
(2 I/O's)
4
clkt, wst, clkr, wsr
2
dig. aud. in
(2 I/O's)
CD input
CDC input
MD input
RDS bit/blk Int.(1 I/O)
RDS
(4 I/O's)
4
X bus 1
X Register
Ram 512
Y Register
Ram 512
Program
Ram 1024
Rom 256
DSP Orpheus Core
including 12 GPIO鈥?s
FM processing,
AM processing,
Traffic mem., Dolby,
Speech synth., etc...
Debug, Test Interface
1 stereo channel
Sample Rate
Converter
DSP Orpheus Core
including 12 GPIO鈥?s
Audio processing,
Sound processing
Debug, Test Interface
5
5
2
4
4
Int
Reset
VDD
GND
Test
(3 I/O's)
(3 I/O's)
SPI
Error corrected RDS blocks
alternatively:
RDS clk, dat, qual, ARI
RDS
DSP1
DSP0
September 1999
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/14

TDA7500 產(chǎn)品屬性

  • STMicroelectronics

  • 數(shù)字信號處理器與控制器 (DSP, DSC)

  • 24 bit

  • 12 KB

  • 43 MHz

  • 43 MIPs

  • 3.3 V

  • + 85 C

  • TQFP-100

  • SMD/SMT

  • - 40 C

  • Tray

  • 90

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