TDA10046HT
Delivering a low cost system solution for DVB-T channel
decoding, the TDA10046HT single chip channel decoder
demonstrates Philips Semiconductors鈥?continuing leader-
ship in digital broadcast reception, offering advanced features
such as adaptive echo cancellation, fast channel scanning and
a unique 鈥楶ulse Killer鈥?algorithm that reduces impulsive noise
disturbances.
Single-chip DVB-T channel
decoder
Semiconductors
The TDA10046HT performs all DVB-T channel decoding functions
from IF input to transport stream output, using an internal DSP core for
synchronization and control.Thanks to its sharp adjacent channel digital
ilter, this single-chip receiver achieves excellent performance with low
cost tuners (one SAW only). It requires only a low cost crystal oscillator
(4 MHz) as a clock source, which can be shared with the tuner.
After
sampling of the 1st or 2nd IF by a 10-bit ADC, the signal is converted to
baseband and passes through the FFT demodulator. Channel frequency
response is then estimated and iltered in both time and frequency
domains, and used to equalize the signal.
correction handles tuner phase noise.
The TDA10046HT implements a number of advanced features including a
high-performance 鈥楶ulse Killer鈥?algorithm to reduce the disturbing effects
of short and strong impulsive noise interference caused by electrical
domestic devices and/or car trafic. For maximum ease of use, the
TDA10046HT features fully automatic transmission parameters detection,
ultra fast scan of the whole UHF/VHF band, and fast zapping facilities.
Evaluation boards are available with most commercial tuners.They are
provided with all the necessary software including a tailored Graphical
User Interface (GUI) that allows easy evaluation and development.
A common phase error
Key features
鈥?2K and 8K COFDM demodulator, fully ETS 300-744 compliant
鈥?TPS and Cell Identiier
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I
鈥?2nd or 1st IF analog input
鈥?On chip 10-bit ADC and PLL
鈥?Single or dual AGC loop (with programmable takeover point)
鈥?Adjacent channel digital iltering (only one external SAW ilter is required)
鈥?Automatic frequency offset detection (鹵1, 2 or 3 standard offsets)
鈥?Dynamic FFT window positioning, and adaptive echo equalization
鈥?Consolidated algorithm for impulsive noise reduction
鈥?DSP based synchronization enables on the ly irmware upgrades
鈥?No extra-host software required
鈥?Fast UHF/VHF band scanning
鈥?Simultaneous tri-state parallel and serial Transport Stream interfaces
鈥?4 GPIO pins with
鈭?/div>
鈥?I
2
C-bus interface
鈥?5V tolerant I/O pins
鈥?Low power consumption (450mW)
鈥?TQFP64 package, CMOS 0.18 碌m technology
C-bus readable
modulator
Applications
鈥?Integrated Digital TV (iDTV)
鈥?Set-Top-Boxes (STB)
鈥?Personal Video Recorder (PVR) with DVB-T reception
鈥?Digital TV PCI card for Personal Computers
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