TC7MET138AFK
TOSHIBA CMOS Didital Integrated Circuit Silicon Monolithic
TC7MET138AFK
3-to-8 Line Decoder
line decoder fabricated with silicon gate C
2
MOS technology. It
achieves the high speed operation similar to equivalent bipolar
schottky TTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 binary select inputs (A, B and C)
determine which one of the outputs (Y0 - Y7) will go low.
When enable input G1 is held low or either G2A or G2B is held
high, decoding function is inhibited and all outputs go high. G1,
G2A, and G2B inputs are provided to ease cascade connection
and for use as an address decoder for memory systems.
The input voltage are compatible with TTL output voltage.
Weight: 0.02 g (typ.)
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (*) pins without
regard to the supply voltage. These structure prevents device destruction due to mismatched supply and
input/output voltages such as battery back up, hot board insertion, etc.
*:
V
CC
= 0 V
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
High speed: t
pd
= 7.6 ns (typ.) (V
CC
= 5 V)
Low power dissipation: I
CC
= 4 碌A(chǔ) (max) (Ta = 25擄C)
Compatible with TTL outputs: V
IL
= 0.8 V (max)
V
IH
= 2.0 V (min)
Power down protection is provided on all inputs and outputs.
Balanced propagation delays: t
pLH
鈮?/div>
t
pHL
Pin and function compatible with the 74 series (74AC/HC/ALS/LS etc.) 138 type.
1
2001-09-12
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