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TC59LM818DMB-40 Datasheet

  • TC59LM818DMB-40

  • MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits N...

  • 57頁

  • TOSHIBA

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TC59LM818DMB-33,-40
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
288Mbits Network FCRAM2
鈭?/div>
4,194,304-WORDS
脳
4 BANKS
脳
18-BITS
DESCRIPTION
Network FCRAM
TM
is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMB is Network
FCRAM
TM
containing 301,989,888 memory cells. TC59LM818DMB is organized as 4,194,304-words
脳
4 banks
脳
18
bits. TC59LM818DMB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM818DMB can operate fast core cycle compared with regular DDR SDRAM.
TC59LM818DMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAM
TM
is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
-33
CL
=
4
t
CK
t
RC
t
RAC
Clock Cycle Time (min)
CL
=
5
CL
=
6
Random Read/Write Cycle Time (min)
Random Access Time (max)
4.5 ns
3.75 ns
3.33 ns
22.5 ns
22.5 ns
235 mA
65 mA
15 mA
TC59LM818DMB
-40
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
210 mA
60 mA
15 mA
I
DD1S
Operating Current (single bank) (max)
l
DD2P
Power Down Current (max)
l
DD6
Self-Refresh Current (max)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fully Synchronous Operation
鈥?/div>
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
鈥?/div>
Differential Clock (CLK and
CLK
) inputs
CS
, FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and
CLK
.
Fast clock cycle time of 3.33 ns minimum
Clock: 300 MHz maximum
Data: 600 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe
Distributed Auto-Refresh cycle in 3.9
碌s
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency
=
CAS
Latency-1
Programable
CAS
Latency and Burst Length
CAS
Latency
=
4, 5, 6
Burst Length
=
2, 4
Organization: 4,194,304 words
脳
4 banks
脳
18 bits
Power Supply Voltage V
DD
:
2.5 V
鹵
0.125V
V
DDQ
: 1.4 V ~ 1.9 V
Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL
Package:
60Ball BGA, 1mm
脳
1mm Ball pitch (P-BGA60-0917-1.00AZ)
Notice: FCRAM is trademark of Fujitsu limited, Japan.
Rev 1.4
2005-10-19
1/57

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