TC58NVG1S3BFT00/TC58NVG1S8BFT00
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
2 GBIT (256M
脳
8 BIT/128M
脳
16 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E
2
PROM) organized as (2048
+
64) bytes/(1024
+
32) words
脳
64 pages
脳
2048 blocks.
The device has a 2112-byte/1056-word static register which allow program and read data to be transferred between
the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single
block unit (128 Kbytes
+
4 Kbytes: 2112 bytes
脳
64 pages).
The TC58NVG1SxB is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
鈥?/div>
Organization
Memory cell array
Register
Page size
Block size
鈥?/div>
鈥?/div>
TC58NVG1S3B
2112
脳
128K
脳
8
2112
脳
8
2112 bytes
(128K
+
4K) bytes
TC58NVG1S8B
1056
脳
128K
脳
16
1056
脳
16
1056 words
(64K
+
2K) words
Modes
Read, Reset, Auto Page Program, Auto Block Erase錛孲tatus Read
Mode control
Serial input/output
Command control
Number of valid blocks
Max 2048 blocks
Min 2008 blocks
Power supply
V
CC
=
2.7 V to 3.6 V
Program/Erase Cycles
100000 Cycles (With ECC)
Access time
Cell array to register
Serial Read Cycle
Program/Erase time
Auto Page Program
Auto Block Erase
Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
25
碌s
max
50 ns min
200
碌s/page
typ.
1.5 ms/block typ.
10 mA typ.
10 mA typ.
10 mA typ.
50
碌A(chǔ)
max
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Package
TC58NVG1S3BFT00 TSOP I 48-P-1220-0.50
TC58NVG1S8BFT00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)
1
2003-10-30A
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