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TC58FVM62A Datasheet

  • TC58FVM62A

  • TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

  • 61頁

  • TOSHIBA

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TC58FVM6(T/B)2A(FT/XB)65
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64MBIT (8M
脳
8 BITS/4M
脳
16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVM6T2A/B2A is a 67108864-bit, 3.0-V read-only electrically erasable and programmable flash
memory organized as 8388608 words
脳
8 bits or as 4194304 words
脳
16 bits. The TC58FVM6T2A/B2A features
commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands
are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The
TC58FVM6T2A/B2A also features a Simultaneous Read/Write operation so that data can be read during a Write or
Erase operation.
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Power supply voltage
V
DD
=
2.3 V~3.6 V
Operating temperature
Ta
= 鈭?0擄C~85擄C
Organization
8M
脳
8 bits/4M
脳
16 bits
Functions
Simultaneous Read/Write
Page Read
Auto Program, Auto Page Program
Auto Block Erase, Auto Chip Erase
Fast Program Mode/Acceleration Mode
Program Suspend/Resume
Erase Suspend/Resume
data polling/Toggle bit
block protection, boot block protection
Automatic Sleep, support for hidden ROM area
common flash memory interface (CFI)
Byte/Word Modes
鈥?/div>
鈥?/div>
Block erase architecture
8
脳
8 Kbytes/127
脳
64 Kbytes
Boot block architecture
TC58FVM6T2A: top boot block
TC58FVM6B2A: bottom boot block
Mode control
Compatible with JEDEC standard commands
Erase/Program cycles
10
5
cycles typ.
Access Time (Random/Page)
V
DD
2.7~3.6 V
2.3~3.6 V
CL = 30 pF
65 ns/25 ns
70 ns/30 ns
CL = 100 pF
70 ns/30 ns
75 ns/35 ns
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Power consumption
10
碌A
(Standby)
15 mA (Program/Erase operation)
55 mA (Random Read operation)
11 mA (Address Increment Read operation)
5 mA (Page Read operation)
Package
TC58FVM6**AFT:
TSOPI48-P-1220-0.50 (weight: 0.51 g)
TC58FVM6**AXB:
P-TFBGA56-0710-0.80AZ (weight: 0.125 g)
鈥?/div>
2003-01-29
1/61

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