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TC55VEM316AXBN Datasheet

  • TC55VEM316AXBN

  • TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GAT...

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  • TOSHIBA

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TC55VEM316AXBN40,55
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VEM316AXBN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7
碌A(chǔ)
standby
current (at V
DD
=
3 V, Ta
=
25擄C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There
are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output
enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access.
This device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. And, with a guaranteed operating extreme temperature range of
鈭?0擄
to 85擄C, the
TC55VEM316AXBN can be used in environments exhibiting extreme temperature conditions. The
TC55VEM316AXBN is available in a plastic 48-ball BGA.
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
鈭?0擄
to 85擄C
Standby Current (maximum):
3.6 V
3.0 V
10
碌A(chǔ)
5
碌A(chǔ)
鈥?/div>
Access Times:
TC55VEM316AXBN
40
Access Time
CE1
Access Time
55
55 ns
55 ns
55 ns
30 ns
40 ns
40 ns
40 ns
25 ns
CE2
OE
Access Time
Access Time
鈥?/div>
Package:
P-TFBGA48-0811-0.75BZ (Weight:
g typ)
PIN ASSIGNMENT
(TOP VIEW)
48 PIN BGA
1
A
B
LB
I/O9
2
OE
UB
PIN NAMES
3
A0
A3
A5
A17
OP
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
6
CE2
I/O1
I/O3
V
DD
V
SS
I/O7
I/O8
NC
A0~A18
CE1
, CE2
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Option
R/W
OE
C I/O10 I/O11
D
E
V
SS
V
DD
I/O12
I/O13
I/O2
I/O4
I/O5
I/O6
R/W
A11
LB ,
UB
I/O1~I/O16
V
DD
GND
NC
OP*
F I/O15 I/O14
G I/O16
H
A18
NC
A8
*:
OP pin must be open or connected to GND.
2002-07-23
1/14

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