TC55VEM208ASTN40,55
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55VEM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by
8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz (typ) and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7
碌A
standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to
various microprocessor system applications where high speed, low power and battery backup are required. The
TC55VEM208ASTN is available in a plastic 32-pin thin-small-outline package (TSOP).
FEATURES
鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
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Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
鈭?0擄
to 85擄C
Standby Current (maximum):
3.6 V
3.0 V
10
碌A
5
碌A
鈥?/div>
Access Times:
TC55VEM208ASTN
40
Access Time
CE
OE
55
55 ns
55 ns
30 ns
40 ns
40 ns
25 ns
Access Time
Access Time
鈥?/div>
Package:
TSOP鈪?2-P-0.50
(Weight:0.22 g typ)
PIN ASSIGNMENT (TOP VIEW)
32 PIN TSOP
PIN NAMES
A0~A18
Address Inputs
Read/Write Control
Output Enable
Chip Enable
Data Inputs/Outputs
Power
Ground
32
R/W
OE
CE
1
16
(Normal)
17
I/O1~I/O8
V
DD
GND
Pin No.
Pin Name
Pin No.
Pin Name
1
A11
17
A3
2
A9
18
A2
3
A8
19
A1
4
A13
20
A0
5
R/W
21
I/O1
6
A17
22
I/O2
7
A15
23
I/O3
8
V
DD
24
GND
9
A18
25
I/O4
10
A16
26
I/O5
11
A14
27
I/O6
12
A12
28
I/O7
13
A7
29
I/O8
14
A6
30
CE
15
A5
31
A10
16
A4
32
OE
2002-08-07
1/11
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