TC55VCM208ASTN40,55
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VCM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by
8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7
碌A(chǔ)
standby
current (at V
DD
=
3 V, Ta
=
25擄C, typical) when chip enable (
CE1
) is asserted high or (CE2) is asserted low. There
are three control inputs.
CE1
and CE2 are used to select the device and for data retention control, and output
enable (
OE
) provides fast memory access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
鈭?0擄
to 85擄C, the TC55VCM208ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VCM208ASTN is available in a plastic 40-pin thin-small outline package
(TSOP).
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using
CE1
and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
鈭?0擄
to 85擄C
Standby Current (maximum):
3.6 V
3.0 V
10
碌A(chǔ)
5
碌A(chǔ)
鈥?/div>
Access Times:
TC55VCM208ASTN
40
Access Time
CE1 Access Time
CE2
OE
Access Time
Access Time
40 ns
40 ns
40 ns
25 ns
55
55 ns
55 ns
55 ns
30 ns
鈥?/div>
Package:
TSOP鈪?0-P-1014-0.50
(Weight:0.30 g typ)
PIN ASSIGNMENT
(TOP VIEW)
40 PIN TSOP
PIN NAMES
A0~A18
Address Inputs
1
40
CE1 , CE2
R/W
OE
LB , UB
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Option
20
(Normal)
21
I/O1~I/O16
V
DD
GND
NC
OP*
*
: OP pin must be open or connected to GND.
Pin No.
Pin Name
Pin No.
Pin Name
1
A16
21
A0
2
A15
22
CE1
3
A14
23
GND
4
A13
24
OE
5
A12
25
I/O1
6
A11
26
I/O2
7
A9
27
I/O3
8
A8
28
I/O4
9
R/W
29
NC
10
CE2
30
V
DD
11
OP
31
V
DD
12
NC
32
I/O5
13
A18
33
I/O6
14
A7
34
I/O7
15
A6
35
I/O8
16
A5
36
A10
17
A4
37
NC
18
A3
38
NC
19
A2
39
GND
20
A1
40
A17
2003-08-11
1/12
TC55VCM208ASTN55相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠商
下載
-
英文版
1 μA Low Dropout Positive Voltage Regulator
-
英文版
IC,SRAM,1KX4,CMOS,DIP,18PIN,PLASTIC
Toshiba
-
英文版
2,048 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA
-
英文版
2,048 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA [T...
-
英文版
8,192 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA
-
英文版
8,192 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA [T...
-
英文版
65,536 bit static random access memory organized as 8,192 wo...
TOSHIBA
-
英文版
65,536 bit static random access memory organized as 8,192 wo...
TOSHIBA [T...
-
英文版
TC5588J_Toshiba.pdf
Toshiba
-
英文版
SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM
TOSHIBA
-
英文版
SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM
TOSHIBA [T...
-
英文版
2,048 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA
-
英文版
2,048 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA [T...
-
英文版
2,048 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA
-
英文版
2,048 WORD X 8 BIT CMOS STATIC RAM
TOSHIBA [T...
-
英文版
32,768 WORD x 9 BIT CMOS STATIC RAM
TOSHIBA
-
英文版
32,768 WORD x 9 BIT CMOS STATIC RAM
TOSHIBA [T...
-
英文版
32,768 WORD x 9 BIT CMOS STATIC RAM
TOSHIBA
-
英文版
32,768 WORD x 9 BIT CMOS STATIC RAM
TOSHIBA [T...
-
英文版
524,228 WORDS x 8 BIT STATIC RAM
TOSHIBA
1
2
3
4
5
6
7
8
9
10
11
12
