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TC55V400AFT-70 Datasheet

  • TC55V400AFT-70

  • 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM

  • 175.15KB

  • 11頁

  • TOSHIBA

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TC55V400AFT-55,-70
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55V400AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16
bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6
V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5
mA
standby
current (at V
DD
=
3 V, Ta
=
25擄C, maximum) when chip enable (
CE1
) is asserted high or (CE2) is asserted low.
There are three control inputs.
CE1
and CE2 are used to select the device and for data retention control, and
output enable (
OE
) provides fast memory access. Data byte control pin (
LB
,
UB
) provides lower and upper byte
access. This device is well suited to various microprocessor system applications where high speed, low power and
battery backup are required. And, with a guaranteed operating extreme temperature range of
-40擄
to 85擄C, the
TC55V400AFT can be used in environments exhibiting extreme temperature conditions. The TC55V400AFT is
available in normal and reverse pinout plastic 48-pin thin-small-outline package (TSOP).
FEATURES
路
路
路
路
路
路
路
Low-power dissipation
Operating: 10.8 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using
CE1
and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
-40擄
to 85擄C
Standby Current (maximum):
3.6 V
3.0 V
7
mA
5
mA
路
Access Times (maximum):
TC55V400AFT
-55
Access Time
CE1
Access Time
-70
70 ns
70 ns
70 ns
35 ns
55 ns
55 ns
55 ns
30 ns
CE2 Access Time
OE
Access Time
路
Package:
TSOP鈪?8-P-1214-0.50 (AFT) (Weight: 0.38 g typ)
PIN ASSIGNMENT
(TOP VIEW)
48 PIN TSOP
PIN NAMES
A0~A17
1
48
CE1
, CE2
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
R/W
OE
LB
,
UB
I/O1~I/O16
24
(Normal)
25
V
DD
GND
NC
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
A15
17
A17
33
I/O3
2
A14
18
A7
34
I/O11
3
A13
19
A6
35
I/O4
4
A12
20
A5
36
I/O12
5
A11
21
A4
37
V
DD
6
A10
22
A3
38
I/O5
7
A9
23
A2
39
8
A8
24
A1
40
9
NC
25
A0
41
10
NC
26
CE1
11
R/W
27
GND
43
12
CE2
28
OE
13
NC
29
I/O1
45
14
UB
15
LB
16
NC
32
I/O10
48
A16
30
I/O9
46
31
I/O2
47
NC
42
44
I/O13 I/O6
I/O14 I/O7
I/O15 I/O8
I/O16 GND
2001-09-04
1/11

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