TC51WKM516AXBN75
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WKM516AXBN is a 33,554,432-bit pseudo static random access memory(PSRAM) organized as
2,097,152 words by 16 bits. Using Toshiba鈥檚 CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device uses dual power supplies(2.6 to 3.3 V for core and 1.7 to 2.2 V for
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports
deep power-down mode, realizing low-power standby.
FEATURES
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Organized as 2,097,152 words by 16 bits
Dual power supplies(2.6 to 3.3 V for core and
1.7 to 2.2 V for output buffer)
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
Page read operation by 8 words
Logic compatible with SRAM R/W (
WE
) pin
Standby current
Standby
70
碌A(chǔ)
Deep power-down standby
5
碌A(chǔ)
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Access Times:
Access Time
CE1
Access Time
75 ns
75 ns
25 ns
30 ns
OE
Access Time
Page Access Time
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Package:
P-TFBGA48-0607-0.75AZ (Weight:
g typ.)
PIN ASSIGNMENT
(TOP VIEW)
1
A
B
LB
PIN NAMES
A0 to A20
A0 to A2
Address Inputs
Page Address Inputs
2
OE
UB
3
A0
A3
4
A1
A4
5
A2
6
CE2
I/O9
CE1
I/O2
I/O4
I/O5
I/O6
I/O1
I/O3
VDD
VSS
I/O7
I/O8
A20
I/O1 to I/O16 Data Inputs/Outputs
CE1
C
D
E
F
G
H
I/O10
VSS
I/O11
I/O12
A5
A17
NC
A14
A12
A9
A6
A7
A16
A15
A13
A10
Chip Enable Input
Chip select Input
Write Enable Input
CE2
WE
VDDQ I/O13
I/O15 I/O14
I/O16
A18
A19
A8
OE
LB ,
UB
V
DD
V
DDQ
GND
NC
Output Enable Input
Data Byte Control Inputs
Power Supply for Core
Power Supply for Output Buffer
Ground
No Connection
WE
A11
(FBGA48)
2002-08-22
1/11
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