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TB5D1MLD Datasheet

  • TB5D1MLD

  • QUAD DIFFERENTIAL PECL DRIVERS

  • 16頁

  • TI

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TB5D1M, TB5D2H
www.ti.com
SLLS579B 鈥?SEPTEMBER 2003 鈥?REVISED MAY 2004
QUAD DIFFERENTIAL PECL DRIVERS
FEATURES
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Functional Replacements for the Agere
BDG1A, BPNGA and BDGLA
Pin-Equivalent to the General-Trade 26LS31
Device
2.0 ns Maximum Propagation Delays
0.15 ns Output Skew Typical Between
鹵
Pairs
Capable of Driving 50-鈩?Loads
5.0-V or 3.3-V Supply Operation
TB5D1M Includes Surge Protection on
Differential Outputs
TB5D2H No Line Loading When V
CC
= 0
Third State Output Capability
-40擄C to 85擄C Operating Temp Range
ESD Protection HBM > 3 kV and CDM > 2 kV
Available in Gull-Wing SOIC (JEDEC MS-013,
DW) and SOIC (D) Packages
DESCRIPTION
These quad differential drivers are TTL input to
pseudo-ECL differential output used for digital data
transmission over balanced transmission lines.
The TB5D1M device is a pin and functional replace-
ment for the Agere systems BDG1A and BPNGA
quad differential drivers. The TB5D1M has a built-in
lightning protection circuit to absorb large transitions
on the transmission lines without destroying the
device. When the circuit is powered down it loads the
transmission line, because of the protection circuit.
The TB5D2H device is a pin and functional replace-
ment for the Agere systems BDG1A and BDGLA
quad differential drivers. Upon power down the
TB5D2H output circuit appears as an open circuit and
does not load the transmission line.
Both drivers feature a 3-state output with a third-state
level of less than 0.1 V.
The packaging options available for these quad
differential line drivers include a 16-pin SOIC
gull-wing (DW) and a 16-pin SOIC (D) package.
Both drivers are characterized for operation from
-40擄C to 85擄C
The logic inputs of this device include internal pull-up
resistors of approximately 40 k鈩?that are connected
to V
CC
to ensure a logical high level input if the inputs
are open circuited.
DW AND D PACKAGE
(TOP VIEW)
FUNCTIONAL DIAGRAM
AO
APPLICATIONS
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Digital Data or Clock Transmission Over
Balanced Transmission Lines
AI
AO
AO
E1
BO
BO
BI
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V CC
DI
DO
DO
E2
CO
CO
CI
AI
AO
BO
BI
BO
CO
CI
CO
DO
DI
DO
E1
E2
ENABLE TRUTH TABLE
E1
0
1
0
1
E2 Condition
0
0
1
1
Active
Active
Disabled
Active
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2003鈥?004, Texas Instruments Incorporated

TB5D1MLD 產(chǎn)品屬性

  • 40

  • 集成電路 (IC)

  • 接口 - 驅(qū)動器，接收器，收發(fā)器

  • -

  • 驅(qū)動器

  • 4/0

  • -

  • 3 V ~ 5.5 V

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC N

  • 管件

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